Layout Engineering Manager

About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade.

The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

Role:

We're seeking a Layout Engineering Manager to take end-to-end ownership of physical implementation for OLIX's next-generation accelerator silicon - from floor-planning and device-level layout through parasitic-aware iteration, sign-off, and silicon bring-up. You'll work in advanced CMOS FinFET nodes on the Cadence Virtuoso platform, partnering with circuit, optical, and digital teams to deliver high-performance analog and mixed-signal blocks at the heart of breakthrough AI hardware.

Responsibilities:

• Architect, plan, and execute full-custom analog and mixed-signal layouts - high-speed data converters, Ser Des front-ends, PLLs/CDRs, LDOs, bandgaps, TIAs, drivers, and high-bandwidth analog front-ends - in advanced CMOS FinFET nodes.
• Own floor-planning, power-grid design, shielding, and signal-integrity strategy for high-speed blocks; partner with circuit designers to meet aggressive PPA, matching, and noise targets.
• Lead block- and chip-level AMS integration: hierarchical assembly, abutment planning, ESD/latch-up strategy, antenna mitigation, and seal-ring/PAD-ring construction.
• Drive physical-verification, parasitic-extraction, and EM/IR-drop sign-off; iterate with designers on post-layout closure across PVT corners.
• Build and own layout automation - SKILL scripts and parameterized Virtuoso PCells (custom inductors, transformers, T-coils, MOM/MIM caps, guard rings, fill structures) - that accelerate the team.
• Own the layout PDK/IP library and design-data workflows: device generators, tech files, version-controlled libraries, GDSII/OASIS stream-out, and foundry hand-off.
• Plan and execute tape-out: ECO management, metal-only revisions, DFM/DFR sign-off, and cross-functional coordination with package, test, and product-engineering teams.
• Lead projects using team comprised of internal and external design-services partners, setting methodology, running design reviews, and unblocking execution.

Skills & Experience:

• 8+ years of full-custom analog and mixed-signal IC layout, with at least 3 different taped-out products containing high-speed analog content (multi-GHz bandwidth, multi-GSPS converters, Ser Des, or equivalent).
• Tape-out experience in advanced CMOS FinFET (16 nm or below); deep familiarity with FinFET-specific design rules, matching, and parasitic implications.
• Expert command of the Cadence Virtuoso platform:
  Layout XL/Suite, Schematic XL, ADE, and constraint-driven / layout-aware flows.
• Strong proficiency with at least one industry-standard physical-verification environment (Mentor Calibre or Cadence Pegasus/PVS) for DRC, LVS, antenna, density, and ERC/PERC; able to ramp on the alternate flow.
• Hands-on with parasitic extraction and EM/IR-drop tools (Calibre xACT/PEX, Quantus QRC, Voltus, Totem, or equivalent) and post-layout closure methodology.
• Working proficiency in SKILL / SKILL++ for layout automation and PCell development; comfort with Python, Tcl, or shell for flow scripting.
• Experience managing libraries and design data in a version-controlled / SOS environment (Cadence Team Workflow, Cliosoft SOS, or equivalent).
• Solid grounding in semiconductor device physics and the analog implications of layout choices.
• Deep working knowledge of analog-layout best practices: device matching (common-centroid, interdigitation, dummy devices), noise isolation (guard rings, deep n-well, substrate-noise separation, supply partitioning), controlled-impedance and differential routing (return-path management, shielding, transmission-line discipline), symmetry, EM/current-density rules, and mitigation of layout-dependent effects (WPE, STI/LOD stress) in advanced nodes.
• Demonstrated leadership and people-management skills - scoping work, running layout reviews, mentoring engineers, and managing external contractors - with excellent cross-functional communication in fast-moving, ambiguous environments.
• Nice to Have Tape-out experience at 7 nm or below, with multi-patterning and color-aware layout. Advanced PCell development for on-chip passives (custom inductors, transformers, T-coils, baluns) and design-rule-aware automation.
• EM simulation of on-chip passives (EMX, Momentum, HFSS, or equivalent) and integration of EM-extracted models into post-layout flows.
• Familiarity with coherent optical links, photonic-electronic co-design, or high-bandwidth…