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DDR Mixed-Signal Circuit Design Engineer

Job in Austin, Travis County, Texas, 78703, USA
Listing for: Apple
Full Time position
Listed on 2026-06-03
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Hardware Engineer, Electrical Engineering
Job Description & How to Apply Below
** Role Number:*
* ** Summary*
* At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? We have an opportunity for a detailed and extraordinarily hardworking PHY Analog/Mixed-Signal Circuit Designer. As a member of our multifaceted group, you will have the unique and great opportunity to shape upcoming products that will delight and inspire millions of Apple's customers every day!

In this role, we are the center of a PHY design effort collaborating with Platform Architecture, Logic Designers, SIPI, Layout, DV and Timing Teams, with a critical impact on delivering best in class PHY designs. You will be required to do transistor level Analog/Mixed-Signal Circuit Designs, working with Layout Teams on the physical implementation of industry leading PHY designs. The ideal candidate will have significant experience in Analog/Mixed-Signal Circuit Design.

** Description*
* As an Analog/Mixed-Signal Circuit Design Engineer, you will be involved with all phases of high-performance PHY designs from architectural concept to delivery of our final GDS.

** Minimum Qualifications*
* + BS and a minimum of 10 years relevant industry experience

** Preferred Qualifications*
* + Proven understanding of all aspects of Analog/Mixed Signal Circuit Design of PHYs. TX, RX, Delay Locked Loops, Phase Interpolators, Delay Lines, Duty Cycle Cor rectors, reference generators, etc.

+ Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able to collaborate with logic design team.

+ Solid understanding of Circuit Verification tools (Simulators, Extraction, EMIR, Noise, SigEM, etc.).

+ Generate block/chip level specifications.

+ Perform block level verification to close the design by meeting performance, power and area specifications.

+ Participate in establishing Design Methodologies to ensure accurate, by construction designs.
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