System -Speed I​/O Validation Engineer

Position: System High-Speed I/O Validation Engineer
This is a system-level validation role within the Mac and Data Center Hardware organization, focused on Ser Des I/O validation across multiple platforms. You will be responsible for setting up and executing high-speed I/O validation, driving electrical compliance bring-ups, and stress testing I/Os in system environments while collecting and analyzing key metrics. The role also includes high-speed validation and electrical compliance testing of I/Os for form-factor systems, as well as validation of high-speed cables and fixtures.

You will work closely with cross-functional teams including system signal integrity, silicon design, and system design to ensure robust and reliable I/O performance. If you have hands-on high-speed lab experience and are eager to grow your expertise in system-level signal integrity validation, we'd love to hear from you!

In this role you will:
Execute high-speed serial I/O validation across multiple platforms. Conduct high-speed electrical compliance testing and organize compliance data reports for comparison against specifications and approval by certified organizations. Troubleshoot and triage issues with compliance test hardware, fixtures, software, and the Device Under Test (DUT). Perform failure analysis and provide feedback to support iterative hardware design and software tunable improvements. Define and develop stress testing methodologies to identify design operating limits of serial I/Os post system integration.

Validate high-speed fixtures, connectors, cables, and platforms I/Os. Develop Python-based scripts to automate data collection and accelerate validation workflows.

M.S. Degree with 3+ years of relevant work experience. Ability to understand and review channel analysis from Signal Integrity EDA tools. Deep knowledge of system-level Ser Des design and analysis skills, including understanding of transmitter and receiver equalization methods (such as FFE, CTLE, DFE, VGA gain), CDR behaviors, link training algorithms, and eye margining tools.

M.S. Degree or B.S. Degree with industry level lab work experience. Familiarity with different aspects of Signal Integrity for high-speed Ser Des, parallel bus, and single-ended signaling. Understanding of high-speed channel characteristics including insertion loss, return loss, crosstalk, and impedance discontinuities. Hands-on experience with high-speed Ser Des validation such as for PCIe, DP, or USB4/TBT. Hands-on experience and familiarity with lab high-speed equipment including oscilloscopes, BERTs, TDR, and VNA/PNA, including calibration methods.