CAD Engineer - PDV
Job in
Austin, Travis County, Texas, 78719, USA
Listed on 2026-06-03
Listing for:
Apple Inc.
Full Time
position Listed on 2026-06-03
Job specializations:
-
Engineering
Systems Engineer, Software Engineer, Electrical Engineering, Hardware Engineer
Job Description & How to Apply Below
Together, you and your team will enable our customers to do all the things they love with their devices. As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and runset development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams.
With good understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, you will develop rule decks from scratch and/or modify existing ones. You will also have opportunities to develop ML/LLM based automations and solutions.
* Develop, improve and maintain various aspects of physical verification flow and methodology
-Coordinate the effort of validating flows, improving for custom checks and data generation
-Work with the design and PD teams to facilitate the chip design process
-Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
-Collaborate with tool vendors and foundries for PDK performance enhancements
Knowledge in Calibre/ICV/Pegasus runset coding Knowledge of ML/LLM is a plus Knowledge of parasitic extraction, SKILL coding, and PnR tools is a plus Previous industry experience in Silicon chip design flows IP/SOC level PDV debug experience in various technology nodes Scripting skills in programming languages such as Python, Perl, Tcl, Shell, Makefile or C
Experience with flow automation and development
Minimum requirement of BS + 3 years of relevant industry experience
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