Signal Integrity Architect

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Company:

Qualcomm Technologies, Inc.

## Job Area:

Engineering Group, Engineering Group Systems Engineering

General

Summary:

Qualcomm Data Center team is developing High performance, Energy efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work!

Our Mission

We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you'll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing reference platforms based on Qualcomm's Snapdragon SoC, delivering a comprehensive solution that includes hardware, software, reference designs, user guides, SDKs, and more.

Position:
Signal Integrity Architect

We are seeking an experienced Signal Integrity Architect (individual contributor) to develop high-performance signal integrity (SI) solutions tailored for advanced server applications. In this role, you will work closely with the platform team and collaborate with cross-functional teams, including software, firmware, packaging, product management, and component suppliers. You will lead the definition, analysis, and verification of SI for high-speed interconnects across die, interposer, package, PCB, and system levels for data center servers.

Key Responsibilities

* Collaborate with SoC, applications engineering, packaging, and system design teams to define and implement system interconnects that meet the unique demands of high-end server environments.

* Provide guidelines and feedback on silicon timing, bump/RDL, package pinout and PCB specifications.

* Develop customer guidelines and define module interfaces/formats for simulation.

* Lead the creation of server-grade SI models, simulations, and final designs.

* Perform early SI analysis on 2.5D/3D structures and establish design guidelines.

* Update and automate design and analysis flows.

* Prepare and present technical documentation and reports to stakeholders, including engineering teams, senior management, customers, and suppliers.

Minimum Qualifications

* Master's degree in Electrical or Computer Engineering, with a specialization in Signal Integrity (SI).

* 6+ years of experience in SI analysis, simulation, and measurement of high-speed digital systems.

* Strong knowledge of SI fundamentals, including power distribution networks (PDN), EMIR, transmission line theory, crosstalk, S-parameters, and channel simulations.

* Expertise in DDR5/LPDDR5X JEDEC specifications and/or Ser Des standards (PCIe, CXL, USB, Ethernet, etc.).

* Experience in developing SI methodologies from die to system, with lab correlation and validation.

* Proficiency with 2D/2.5D/3D EM simulation tools such as ANSYS HFSS Cadence Sigrity, Dassault Systèmes CST, Keysight ADS, and Synopsys' HSPICE.

* Hands-on experience creating complex SI models and performing both frequency and time-domain simulations.

* Proficiency in Unix/Linux environments and experience with EDA tools through scripting.

* Strong knowledge of packaging and PCB technologies, design, and manufacturing processes.

* Familiarity with 2.5D/3D packaging technologies, such as CoWoS, InFo, EMIB, and RDL.

* Hands-on experience with electrical validation and compliance testing using tools like VNAs, oscilloscopes, spectrum analyzers, PCIe/I2C analyzers, traffic generators, TDR, and differential probes.

* Proven ability to work independently and collaboratively within a cross-functional team environment.

* Strong technical documentation skills and excellent written and verbal communication.

Preferred Qualifications

* Ph.D. in Electrical or Computer Engineering, specializing in SI.

* 10+ years of experience in SI analysis, simulation, and measurement of high-speed digital systems.

* In-depth understanding of computational electromagnetics and transmission line theory.

* Proficiency in DDR5 and LPDDR5X timing budgets, jitter analysis, and PHY design/link analysis.

* Experience with SI simulation for PCIe Gen6+, multi-gigabit serial buses (112

Gbps+), UCIE, etc.

*…