Lead Diagnostics Software Engineer, ATE Integration

Lead/Principal Diagnostics Engineer

As the semiconductor industry pivots toward complex chiplet architectures and hyper-dense data center accelerators, the economics of quality necessitate shifting validation earlier in the production lifecycle. This role will shift post‑silicon software validation frameworks and System‑Level Tests (SLT) directly into Automated Test Equipment (ATE) and Wafer Sort environments.

• Strategic Technical Leadership:
  Define the technical roadmap, architecture, and deployment strategy for migrating post‑silicon SLT and functional GFX IP feature diagnostics onto wafer sort and ATE hardware configurations.
• Pattern Generation & Conversion:
  Architect and develop software utilities and pipelines to convert functional diagnostic sequences, register configurations, and compute workloads into cycle‑accurate vector formats (e.g., STIL, WGL, or proprietary tester formats) compatible with high‑end ATE testers.
• Cross‑Domain
  
  Collaboration:
  
  Serve as the primary technical liaison between the GFX/Compute Diagnostics team, Product/Test Engineering, and Design‑for‑Test (DFT) teams.
• Platform Integration & Emulation:
  Build deterministic, tester‑friendly models that emulate host behaviors on ATE hardware by analyzing platform‑level hardware/software dependencies such as sideband management interfaces, firmware, and power management behaviors.
• Test Coverage & Cost Optimization:
  Maximize structural and functional test coverage for data center GPU IPs while optimizing tester execution times and reducing test costs.

• Proven industry experience in silicon engineering spanning post‑silicon validation, product engineering, diagnostics development, or structural/functional test generation.
• Strong programming background in C/C++ and Python, with knowledge of bare‑metal or driver‑level programming, registers, firmware interactions, and system memory maps.
• Hands‑on experience with production‑grade ATE platforms (e.g., V93000, Ultra
  
  FLEX) and structural/functional testing at wafer sort or final test levels.
• Expertise in structural pattern generation, vector timing, clock domains, and diagnostic patterns (e.g., functional vectors, BIST/MBIST, or scan compression).
• Experience with high‑volume manufacturing challenges in data center architectures, including high‑power profiles, HBM integration, and multi‑die chiplet interconnect protocols such as UCIe.
• Deep understanding of GFX and compute architectures, with a track record of designing diagnostic test cases that maximize coverage and detect silicon issues early.
• Knowledge of AI/ML principles and experience applying LLM or ML models in applications.
• Experience working in a Dev Ops environment such as Git Hub with CI/CD pipelines.
• Excellent problem‑solving abilities and keen attention to detail.

• Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

Austin, TX
Not eligible for visa sponsorship.

AMD is an equal opportunity, inclusive employer and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. Applications will be accommodated under applicable laws throughout all recruitment stages.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available upon request.

This posting is for an existing vacancy.