Formal Verification Engineer

Overview

At AMD, the Infinity Fabric network on the chip verification team is growing and looking for qualified candidates to help verify configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed for AI/ML, Client, Server, Graphic Accelerator, and Semi-Custom markets.

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The Role:

The Infinity Fabric network on the chip verification team is growing and looking for qualified candidates to help verify our configurable switches and die-to-die interconnect.

The Infinity Fabric network on the chip verification team is growing and looking for qualified candidates to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed for AI/ML, Client, Server, Graphic Accelerator, and Semi-Custom markets.

Team is seeking a highly skilled and motivated person to join our verification team. In this role, you will drive formal verification efforts across complex hardware designs, applying rigorous mathematical methods to prove design correctness and find corner-case bugs that escape simulation. You will serve as a subject matter expert in formal verification methodologies, mentor junior engineers, and collaborate with RTL designers, simulation-based verification engineers, and architects to shift verification left and improve overall design quality.

• Develop and execute formal verification strategies using VC Formal and/or Jasper Gold for property checking (FPV), connectivity checking (CC), register verification (FRV), and sequential equivalence checking (SEQ)
• Write, review, and debug System Verilog Assertions (SVA) — including assumptions, assertions, and cover properties — to verify complex design behaviors
• Drive convergence on formal proofs by applying abstraction techniques, complexity reduction strategies, and assume-guarantee reasoning
• Collaborate with RTL designers and architects to define verification plans that incorporate formal methods alongside simulation-based approaches
• Identify and pursue opportunities to apply formal verification to new design blocks, championing a "formal-first" or "shift-left" verification strategy
• Develop reusable formal verification infrastructure, including constraint libraries, parameterized property templates, and automated regression flows
• Mentor and guide MTS and junior engineers in formal verification techniques and best practices

• Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)
• Strong proficiency in System Verilog Assertions (SVA) and formal property specification
• Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
• Familiarity with scripting languages (TCL, Python, Perl) for flow automation
• Minimum 8+ years of experience in design verification with a strong focus on formal verification

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Location: Austin, TX;
Boston, MA and Santa Clara, CA

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.