Server Performance Architect

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary.

We are seeking an outstanding technical contributor to help architect, validate and optimize performance of new features through full‑chip simulation and emulation platforms for AMD‑based next‑generation servers. As a Server Systems Performance Architect within the Server Performance Group, you will identify opportunities to optimize server silicon for throughput and latency across CPU, Data Fabric, Memory subsystem and I/O. You will validate and analyze performance of design features in pre‑silicon environments, correlate profiling data with AMD performance models, and share insights to guide the next generation of server CPUs.

• Team Dynamics
  • Foster a culture of innovation, technical rigor, and continuous improvement.
  • Collaborate with architecture, u‑arch, RTL, performance modeling, firmware and software teams to define and validate performance KPIs.
• Performance Analysis & Correlation
  • Develop and execute performance verification plans targeting IPC, latency, throughput and power efficiency.
  • Debug performance outliers through Performance Monitoring Counters (PMC).
  • Drive correlation between RTL and performance models, ensuring architectural intent is met.
  • Analyze performance bottlenecks using simulation, emulation and silicon data.
• Toolchain & Methodology
  • Build and maintain scalable, modular performance verification infrastructure.
  • Provide emulation‑based performance set‑up and debug, enabling early performance validation.
  • Integrate performance regression, profiling and analysis flows using industry‑standard and custom tools.
  • Collaborate with compiler and OS teams to ensure software stack alignment with hardware performance goals.
• AI‑Driven Infrastructure
  • Develop AI/ML‑based infrastructure to automate performance analysis, anomaly detection and efficiency improvements.
  • Leverage data‑driven techniques to optimize verification coverage and reduce debug cycles.
• Cross‑Functional Collaboration
  • Partner with x86 architecture, RTL design, physical design and software teams to ensure performance targets are met.
  • Influence design decisions through data‑backed performance insights.
• Industry Awareness
  • Stay current with trends in CPU architecture, performance modeling and verification technologies.
  • Evaluate and adopt emerging tools and techniques to maintain a competitive edge.

• 5+ years of industry experience with performance modeling and simulation tools (e.g., cycle‑accurate simulators, emulators) and a strong background in CPU microarchitecture, performance analysis and system‑level performance verification.
• Familiarity with PMC DV, latency and throughput validation, emulation platforms and performance debug flows.
• Deep understanding of x86 ISA, microarchitecture and performance metrics.
• Experience developing performance test suites, performance triage tools and simulation/emulation infrastructure.
• Expertise in performance analysis tools, correlation techniques and workload optimization.
• Strong analytical and problem‑solving skills with a data‑driven mindset.
• Excellent communication and interpersonal skills.
• Deep knowledge of modern out‑of‑order CPU cores, memory subsystems and performance modeling is a plus.
• Familiarity with performance benchmarks such as SPEC CPU.
• Experience with ML/AI techniques/frameworks for performance triage, infrastructure automation and prediction is a plus.
• Exposure to high‑performance computing, virtualization or server‑class CPUs.
• Background in hardware/software co‑design and performance‑aware compiler optimizations.
• Familiarity with pre‑silicon and post‑silicon debug methodologies.

• Have executed emulation‑based functional and performance verification for multi‑million‑gate SoC designs.
• Strong exposure to RTL coding and SoC bring‑up debug.
• Exceptionally grounded in systems architecture across CPU, memory, storage…