SoC Design Engineer

Overview

As a SoC Logic Design Engineer at Intel, you will play a pivotal role in shaping the future of System on Chip (SoC) designs. This position provides an opportunity to contribute to the development of world‑class technology solutions that drive innovation across diverse industries. You will develop high‑quality logic designs, write register transfer level (RTL) models, and conduct thorough simulations to ensure optimal functionality.

Your contributions directly impact Intel’s products by enabling power‑efficient, high‑performance, and scalable solutions that meet or exceed market demands.

• Develop logic designs and RTL code for SoC designs in alignment with architectural and microarchitectural specifications.
• Integrate logic for IP blocks and subsystems into full‑chip SoC designs.
• Conduct quality checks across RTL, timing, power, and area convergence, addressing design integrity for physical implementation.
• Optimize logic designs to meet stringent power, performance, area, and timing goals.
• Review verification plans and ensure correctness of tested design features.
• Resolve RTL test failures by implementing corrective measures to guarantee feature correctness.
• Apply secure development practices to mitigate security threats and meet secure design objectives.
• Collaborate with IP providers to integrate and validate IP at the SoC level.
• Drive compliance with quality assurance standards to enable seamless IP/SoC handoffs.

• Demonstrated ability to work collaboratively across teams and communicate effectively in complex technical environments.
• Passion for innovation, problem‑solving, and continuous learning within SoC design.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a STEM related field.
• 3+ years of experience in microarchitecture development, RTL coding, or logic design.
• Experience in clock domain crossing techniques, low‑power design methodologies, and SoC clocking structures.
• Experience with tools and strategies for RTL design, SoC integration, and physical implementation optimization.

Preferred Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or a STEM related field.
• Experience with secure development practices for secure design implementation.
• Experience in SoC Builder and Network‑on‑Chip (NoC) architectures.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)
Primary

Location:

US, Texas, Austin
Additional Locations: (none listed)

The Central Engineering Group (CEG) focuses on customer‑driven, end‑to‑end solutions across product enablement, custom ASIC, and foundry enablement.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, gender, age, disability or other protected characteristics.

We offer a competitive compensation package that includes base salary, stock bonuses, and benefit programs such as health, retirement, and vacation. Up to $ USD per annum based on location and experience.

Hybrid work model allowing on‑site and off‑site work.

Intel does not charge candidates any fees during the hiring process. Please report any request for payment to your recruiter.