Principal Datacenter GPU Lead Power Constrained Performance Architect

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AMD’s Datacenter Performance Group is seeking a senior Power & Performance Architect to drive the Power Constrained Performance of our industry‑leading AI/ML/HPC GPUs. The role will involve owning the Perf@Power attainment of a leading generation of our Instinct accelerators, providing cross‑functional leadership for a virtual team that drives all aspects of Perf@Power attainment, including pre‑Si modeling, post‑Si correlation, workload analysis, setting PPA targets and driving attainment, power/perf roll‑ups and reporting, methodology innovations and development.

Passion for performance and power efficiency, influence without authority, and excellent communication skills are key ingredients for success in this role.

• Own power‑constrained performance modeling, projections, implementation target setting and attainment tracking from Concept‑exit (pre‑si) to Product launch (post‑si) for AMD Instinct AI/ML/HPC accelerators
• Work with business unit and product architecture to define product configurations, capabilities and P&P targets
• Cross‑functionally lead P&P attainment by working with various engineering functions including SOC architecture, System Design, IP Design, Circuit Design, Foundry team, CAD, Physical Design, Software, Power Management, Post‑si validation
• Roll‑up Power/Performance readouts, present in executive forums, and motivate cross‑functional teams on power efficiency improvements
• Mentor junior engineers and develop skillsets and methodologies in the team for important PPA domains such as Power Modeling at various stages of SoC development, Cdyn/Leakage/STA/Area trade‑offs and attainment, Silicon Power/Performance debug, Post‑Si calibration of models, and workload power analysis

• Background in Computer Architecture, Processor/Accelerator development
• Experience in Power/Performance projections, modeling and optimization at SoC or System level
• Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V‑F curves, p‑states, on‑die voltage regulation, clock integrity, etc.)
• Familiarity with post‑silicon power/performance debug and model correlation
• Fluency in communicating with various engineering teams, business leads and executive management
• Knowledge of DL/ML/LLM/MoE workloads will be a bonus

• Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or related field

This role is not eligible for visa sponsorship.

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.