Senior MXS Verification engineer

For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Sr Mixed signal verification engineer.

Key Responsibilities:

• Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications.
• Create behavioural models for analog blocks in accordance with guidelines provided by analog designers.
• Write, execute, and debug test benches using UVM methodology and System Verilog code for mixed-signal blocks.
• Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models.
• Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs.

Minimum Qualifications

• 10+ years of experience
• Experience in Behavioural Modelling (BM) of Analog design for digital verification
• Experience in Verilog/System Verilog coding
• Experience in Virtuoso Schematics tools
  
  Basic knowledge in Analog design

Preferred Qualifications

• Experience in UVM
• Experience in both Synopsys and Cadence tools is an advantage

Additional Skills

• Verification Methodologies and Tools
  :
  Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
• Collaborative Environment
  :
  Ability to verify Analog/mixed-signal designs in a collaborative team environment.
• Communication
  :
  Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.