Lead Senior Design Engineer – AI SoC Development

Intel’s AI SoC organization develops cutting‑edge products powering a wide range of AI applications—from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast‑paced environment with abundant learning opportunities, this is your chance to shape the future of AI hardware.

As a Lead Senior Design Engineer – AI SoC Development, you will be responsible for defining, implementing, and validating complex SoC IP blocks and subsystems, ensuring they meet stringent power, performance, and security requirements. You will collaborate across architecture, verification, and physical design teams to deliver high‑quality silicon for next‑generation AI solutions.

• Architectural Leadership:
  Evaluate trade‑offs across features, performance targets, power constraints, and system limitations.
• Microarchitecture & RTL Development:
  Define and document microarchitecture for complex SoC IP blocks; implement RTL in Verilog/System Verilog, integrate at top level, and deliver synthesis‑ and timing‑clean designs.
• Verification
  
  Collaboration:
  
  Partner with verification teams to ensure comprehensive coverage and robust validation of all design aspects.
• Timing & Physical Design Support:
  Develop and maintain timing constraints; guide physical design teams on synthesis, timing closure, and formal equivalence checks.
• Silicon Bring‑Up:
  Drive post‑silicon validation, debug, and performance analysis.
• Mentorship & Methodology:
  Mentor junior engineers and contribute to best practices for design methodology and quality.

• Perform quality checks across RTL, timing, and power convergence.
• Apply secure development practices to address security threat models and objectives.
• Collaborate with IP providers for integration and validation at the SoC level.
• Drive compliance for smooth IP‑to‑SoC handoff.

• Ability to lead projects, work cross‑functionally, and deliver under tight schedules.
• Strong communication skills and a collaborative mindset.

Minimum Qualifications

• Bachelor’s or master’s degree in electrical engineering, computer engineering, computer science, or related field with 10+ years of experience.
• 7+ years of experience in RTL design and implementation for ASIC/SoC development.

Preferred Qualifications

• Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure.
• Hands‑on experience with SoC system integration and multicore CPU subsystem design.
• Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures.
• Expertise in high‑speed and low‑power design techniques.
• Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization.
• Familiarity with industry‑standard EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).

Experienced Hire

Shift 1 (United States of America)

US, California, Folsom

• US, California, Santa Clara
• US, Texas, Austin

• Competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Annual salary range for US jobs: $- USD.
• Hybrid work model allowing employees to split time between on‑site and off‑site.

This role is a Position of Trust. You must consent to and pass an extended background investigation, which includes (subject to country law) extended education, SEC sanctions, and additional criminal and civil checks.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.