Technical IP management

Job Description

We are seeking a highly technical IP Manager to serve as the central nervous system for our silicon IP ecosystem. In this role, you will bridge the gap between high-level SoC architecture and execution, managing the full lifecycle of internal and external IPs. You are not just a coordinator; you are a technical leader capable of assessing IP roadmaps, defining development processes, and driving cross‑functional teams to deliver high‑quality silicon components.

You must excel at leading through influence, managing complex dependencies between internal engineering groups and third‑party vendors without direct line‑reporting authority.

• Requirements & Roadmap Management:
  Translate SoC architectural needs into detailed technical IP specifications. Drive the long‑term IP roadmap, ensuring alignment with future technology nodes and market requirements (e.g., RISC‑V, NPU, Automotive Networking). Work with remote IP execution reams to streamline roadmaps
• IP Development Process:
  Establish, document, and enforce a standardized IP Lifecycle Process, covering everything from initial "Make vs. Buy" analysis and RTL handoff to final silicon validation and IP tagging/versioning.
• Third‑Party Vendor Management:
  Work with third party IP Program management Act as the primary technical interface for external IP providers. Manage / evaluate requirements and schedule conflicts and drive technically superior outcomes.
• Cross‑Program Coordination:
  Drive synchronization between multiple internal IP teams (Compute, High‑Speed I/O, Infrastructure) and SoC program managers to ensure timely delivery of IP "drops" for top‑level integration.
• Technical Governance:
  Lead technical reviews to assess IP maturity, PPA (Power, Performance, Area) compliance, and integration readiness. Ensure all IPs adhere to the "complete design flow" (LINT, CDC, Synthesis, DFT).
• Influence & Leadership:
  Lead matrixed teams across global sites. Resolve technical conflicts between IP roadmaps and project‑specific needs through expert negotiation and technical justification.

• Education:
  
  Bachelor’s or Master’s in Electrical Engineering or Computer Engineering, an MBA or PMP certification is a plus but must be accompanied by strong technical roots.
• Experience:
  
  18–20+ years in SoC Design, IP Development, or Technical Program Management. Must have a strong background in RTL design or Architecture.
• Technical Breadth:
  Deep understanding of common IP blocks (PCIe, Ethernet, CPU cores, Memory Controllers) and SoC infrastructure (Bus fabrics, Clock/Reset, Power Management).
• Process Expertise:
  Proven track record of defining or improving hardware development methodologies (e.g., ISO 26262 compliance, UVM verification flows).
• Third‑Party Savvy:
  Experience managing major IP vendors (e.g., Synopsys, Cadence, Arm) and navigating licensing/delivery milestones.
• Soft Skills:
  
  Exceptional communication skills with the ability to distill complex technical roadblocks into actionable executive‑level summaries.

Renesas Electronics is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual‑use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons; the decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.