Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration - Annapurna Labs; AWS

Utility Computing (UC) is a key organization within Amazon Web Services (AWS) that delivers foundational cloud services such as Simple Storage Service (S3), Elastic Compute Cloud (EC2), and advanced Innovations across Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services. The Cloud‑Scale Machine Learning Acceleration team, a part of UC, designs and optimizes silicon and software for AWS’s machine‑learning inference servers, including the custom Inferentia platform.

• Integrate multiple subsystems into a top‑level System on Chip (SoC) and validate correct clock, reset, functional, and DFT signal routing.
• Design and deliver high‑performance, area‑ and power‑efficient Register‑Transfer Level (RTL) logic that meets design targets and specifications.
• Analyze microarchitecture and system architecture to make informed trade‑offs based on features, power, performance, or area requirements.
• Develop micro‑architectural blocks, implement System Verilog RTL, and produce synthesis‑ and timing‑clean designs with constraints.
• Perform lint and clock‑domain crossing checks to ensure design quality.
• Collaborate with architects, designers, verification, pre‑ and post‑silicon validation, synthesis, timing, and back‑end teams throughout the design process.
• Apply Python scripting for automation tasks and debugging of RTL test failures.
• Maintain a "Learn and Be Curious" mindset and contribute to the team’s continuous improvement.

• Bachelor’s degree in Electrical Engineering or a related field.
• 5+ years of RTL design experience for SoC-level architectures.
• 5+ years of experience in VLSI engineering.
• Proficiency with code quality tools such as Spyglass, Lint, or Clock‑Domain Crossing (CDC) utilities.

• Master’s degree or Ph.D. in Electrical Engineering or a related field.
• Experience scripting for automation (Python, Perl, Ruby).
• Strong analytical skills, attention to detail, and effective communication abilities.
• Experience with micro‑architecture, System Verilog RTL, assertions, and SDC constraints.
• Familiarity with data‑path design, interconnects, and AXI protocol.

Locations:
Cupertino, CA (USD 183,000 – 247,600 annually);
Austin, TX (USD 159,200 – 215,300 annually). Base salary is supplemented with sign‑on payments and Restricted Stock Units (RSUs). Final compensation is influenced by experience, qualifications, and location. Benefits include health, dental, vision, prescription, life insurance, EAP, mental health support, and Flexible Spending Accounts, as well as 401(k) matching, paid time off, and parental leave.

Amazon is an equal‑opportunity employer and does not discriminate on the basis of protected veteran status, disability, or any other legally protected status.