Server Power Management Sr. Staff Architect
Listed on 2026-07-18
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Engineering
Systems Engineer, Hardware Engineer, Test Engineer, Electrical Engineering
Company
Qualcomm Technologies, Inc.
Job AreaEngineering Group, CPU Engineering
LocationsAustin, Santa Clara, Portland
General SummaryQualcomm Data Center team is developing high‑performance, energy‑efficient server solutions for data center applications. We seek highly talented, innovative, teamwork‑oriented individuals for our cutting‑edge technology work.
Our MissionWe are dedicated to transforming the industry by reimagining silicon and developing next‑generation computing platforms. By joining our team, you’ll collaborate with world‑class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing server‑class high‑performance solutions that are highly optimized for the needs of the server product.
Position:Server Power Management Architect
We seek a highly experienced Server Power Management Architect. If you possess a deep understanding of Server SoC designs and have a passion for architecting and designing complex, high‑performance, low‑power designs at advanced process nodes, we would be pleased to hear from you. This critical role involves defining the architecture of the end‑to‑end power management of a Server SoC by collaborating with other CPU and SoC architects to optimize overall Power, Performance, and Thermal efficiency.
The ideal candidate will have extensive knowledge of CPU and SoC power management architecture for data‑center SoCs, including experience in microarchitecture and design of power management components for a modern SoC. Strong analytical, problem‑solving, and communication skills are essential for excelling in this position.
Minimum Qualifications- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- Over 10 years of experience in power management of CPU and/or SoCs, and at least 5 years of experience with a high‑performance server chip.
- Strong expertise in power management of a high‑performance system including management of active power, idle low power, and silicon/system limits.
- Experience in power delivery systems including multi‑phase bucks and LDOs.
- Strong fundamentals in digital ASIC design and power of CMOS circuits.
- Strong technical documentation skills, along with excellent written and verbal communication abilities.
- Master's in Computer Science/Engineering, Electrical Engineering, or related field.
- 15+ years in CPU and/or SoC architecture.
- Experience in TDP (thermal design power) capping and control.
- Experience in measurement and management of over‑current and voltage droop events.
- Experience in developing solutions for power and performance telemetry.
- Strong understanding of silicon test methodologies for power and thermal optimization.
- Experience in designing SoCs for systems using off‑the‑shelf PMICs.
- Proven track record in hyperscale data center solutions.
- Familiarity with high performance and low power design techniques.
- Work with chip architects to understand architecture concepts and high‑level system requirements.
- Collaborate with HW, SW and FW architects to develop an optimal end‑to‑end power management architecture.
- Execute system‑level power modeling for server use cases and analyze trade‑offs.
- Drive convergence of SoC and board power grid definition.
- Architect SoC and system‑level power rail sequencing.
- Collaborate with Thermal engineers to optimize implementation.
- Communicate effectively and work in a dynamic environment with top‑level engineers and technologists.
- Create detailed architecture specification documents.
$ – $. This scale reflects the broad, minimum to maximum pay for this job code at the posted location. Salary is only one component of total compensation. Additional benefits include a competitive discretionary bonus program and annual RSU grants. Full benefits details are available through Qualcomm’s US benefits portal.
EEO EmployerQualcomm is an equal‑opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
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