CPU Core Design Verification Engineer

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As a Core Design Verification Engineer, you will be responsible for verifying new and existing microarchitectural features in Amd's next-generation x86 CPU cores. This role focuses on unit- and core-level verification using a C++ and Verilog/System Verilog-based environment, with an emphasis on robust testbench architecture, reusable verification agents, and high-quality coverage closure.

You will work closely with architects, RTL designers, and fellow verification engineers to ensure architectural intent is correctly implemented and thoroughly validated. Success in this role requires strong computer architecture fundamentals, the ability to reason about complex microarchitectural interactions, and a self-motivated approach to solving ambiguous and challenging verification problems.

You have a strong passion for computer architecture and processor microarchitecture and enjoy working at the intersection of hardware and software. You are a self-motivated problem solver who takes ownership of verification quality end-to-end, from test planning through debug and coverage closure.

You value clean, scalable verification environments and understand the importance of sound testbench and agent architecture. You collaborate effectively across teams and time zones, communicate clearly, and continuously look for ways to improve verification efficiency, quality, and methodology.

• Collaborate with CPU architects and RTL designers to understand microarchitectural features, corner cases, and verification requirements
• Define and own unit- and core-level test plans, including stimulus, checking, and functional coverage strategies
• Design, implement, and maintain C++-based and System Verilog-based test benches, with a focus on modular, reusable verification agent architectures
• Develop directed and constrained-random C++ tests to validate architectural behavior and stress complex microarchitectural interactions
• Write and maintain System Verilog assertions and functional coverage models
• Debug simulation failures, identify root cause, and work cross-functionally to resolve RTL, firmware, or testbench issues
• Drive functional and code coverage closure, identify verification gaps, and improve stimulus and checking as needed
• Contribute to verification infrastructure, workflows, and methodology improvements, including debug efficiency and simulation performance
• Mentor junior engineers and contribute to a culture of high-quality, scalable verification

• Experience with CPU or complex microprocessor verification, preferably x86-based designs
• Strong background in computer architecture and microarchitecture concepts
• Proficiency in C++ for verification test development and infrastructure
• Proficiency in Verilog and System Verilog, including assertions and functional coverage
• Experience designing and maintaining testbench architectures and verification agents
• Strong debug skills using Verilog/System Verilog simulation tools
• Familiarity with constrained-random testing and coverage-driven verification
• Experience working in Linux-based development environments
• Exposure to x86 assembly language or low-level architectural programming is a strong plus
• Scripting experience (Python, Perl, shell, Makefile) for automation and workflow support
• Experience leveraging Ai-assisted or agent-based development tools to improve verification productivity, including test generation, debug assistance, code refactoring, or workflow automation
• Ability to integrate Ai-assisted tooling into C++ and System Verilog verification environments while maintaining code quality, correctness, and debuggability
• Interest in exploring and advancing verification and software development methodologies, including new tools, workflows, and automation techniques that improve verification efficiency and quality

Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or Computer Science

Austin, TX

This role is not eligible for visa sponsorship

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