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Principal Verification Lead - UVM & Memory Controllers

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Cadence Design Systems
Full Time position
Listed on 2026-07-18
Job specializations:
  • Engineering
    Test Engineer
Salary/Wage Range or Industry Benchmark: 140000 - 210000 USD Yearly USD 140000.00 210000.00 YEAR
Job Description & How to Apply Below

Cadence Design Systems in Austin is seeking a senior verification lead to enhance the functional verification environment, support customer configurations during regressions, and drive quality metrics through functional and code coverage efforts.

The role requires 10–12 years in design verification, strong UVM-based experience, and familiarity with DDR/LPDDR and AXI/CHI-E interfaces. Based in Austin, this position offers a challenging opportunity to impact advanced verification flows.

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