AI SoC Hardware Architect

AI SoC Hardware Architect

Location:

Austin, TX. Cross‑functional leadership across Model Engineering, AI Infrastructure, and Silicon Architecture.

Most chip programs require seamless translation between AI models, silicon hardware, and infrastructure. Disconnected handoffs bleed performance. This role eliminates that translation gap, ensuring every hardware investment aligns with workloads and software stacks.

As Principal AI Hardware Architect, you own the technical contract between AI workloads, software systems, and custom silicon. Your decisions are realized on silicon; you develop performance models, guide compute and memory hierarchy choices, and ensure the software stack can exploit hardware advances.

• Workload‑to‑Architecture Translation:
  Analyze real‑world test cases and translate them into concrete hardware requirements.
• Performance Modeling Ownership:
  Build analytical, simulation, and cycle‑approximate models that dictate compute investments and feature prioritization.
• Real Workload Validation:
  Profile workloads on current and future platforms, identify bottlenecks, and feed findings into design cycles.
• Strategic Technical Translation:
  Align hardware architects, AI researchers, and infrastructure teams, grounding decisions in measurable constraints.

• AI/ML Systems depth:
  Deep understanding of inference systems, quantization, deployment constraints, and silicon utilization costs.
• Silicon Architecture fluency:
  Experience with processor, accelerator, or custom silicon architectures, performance trade‑off analysis, and on‑chip interconnects.

• 12+ years of industry experience across AI, systems, or silicon.
• Proven experience at the intersection of hardware and intelligent compute systems.
• Hardware/software co‑design leadership across full product cycles.
• Demonstrated performance modeling expertise (analytical, simulation, or cycle‑approximate).
• Track record of influencing architectural and product decisions across multiple technical organizations.
• Exceptional written communication and technical specification ability.
• Strong Python and C++ skills.

• Experience with custom silicon, accelerators, or advanced hardware platforms.
• Prior involvement in ISA definition, memory hierarchy design, or accelerator roadmap decisions.

• Competitive salary commensurate with experience.
• Health, dental, and vision benefits with company‑matched contributions.
• 401(k) plan with company match and stock purchase opportunity.
• Paid time off: vacation, personal days, holidays, sick and volunteer time.
• Maternity and parental leave benefits.

Ericsson is proud to be an Equal Opportunity employer.