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EDA Tools Hardware Engineer

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Intel Corporation
Full Time position
Listed on 2026-07-19
Job specializations:
  • Engineering
    Hardware Engineer, Electronics Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 141910 - 269100 USD Yearly USD 141910.00 269100.00 YEAR
Job Description & How to Apply Below

Job Title: EDA Tools Hardware Engineer

Location: US, California, Santa Clara (Primary); additional locations include Folsom, Oregon Hillsboro, Texas Austin

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Overview

Join Intel's world‑class team as an EDA Tools Hardware Engineer, where you will play a pivotal role in shaping the future of silicon innovation. This position directly contributes to the enablement and adoption of cutting‑edge hardware design tools, flows, and methodologies. Your work will enhance the efficiency of design processes and optimize power, performance, and technology node advancements. As part of Intel, you will collaborate with EDA vendors, define next‑generation design tools, and contribute to groundbreaking innovations that enrich lives worldwide.

Responsibilities
  • Develop and maintain full‑chip physical implementation flows, including floor planning and partitioning strategies, hierarchical block integration, chip‑level placement and routing coordination, power grid planning and analysis, and clock tree synthesis (CTS) strategy integration.
  • Enable scalable SoC assembly flows for multi‑block and multi‑power domain designs, defining methodology for hierarchical design reuse and integration.
Qualifications
  • Minimum one of the following:
    Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field with at least 6+ years of experience; or Bachelor's with 6+ years;
    Master's with 4+ years; or PhD with 2+ years.
  • Physical design fundamentals (placement, routing).
  • Clock tree synthesis (CTS) experience.
  • Full‑chip integration methodologies using Innovus.
  • Experience with large SoC or multi‑block design implementation flows.
  • Experience scripting and automation skills in Linux environments.
Preferred Qualifications
  • Static timing analysis (STA).
  • Power grid design and IR drop concepts.
Benefits and Compensation

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs including health, retirement, and vacation.

Annual salary range for this position in the United States: $141,910–$269,100 USD.

Work Model

This role will be eligible for our hybrid work model, allowing employees to split their time between working on‑site at their assigned Intel site and off‑site.

Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Hiring Practices

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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