VP of Systems

About Neurophos

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

The VP of Systems owns the development of our inference servers and rack and is responsible for the electrical, mechanical, and systems engineering aspects of designing and delivering our full-scale products. This role will own system development from the boards and interconnect through the end-to-end power and high-speed-channel budgets that make the design close, to full system bring-up. Everything needed to connect our optical processing units (OPUs) together, integrate them into the rack, and ensure the system boots, runs, and passes qualification.

Reports to the SVP of Engineering.

Austin, TX or Sunnyvale, CA. Full-time onsite position.

• Boards, interconnect & fabric: the accelerator baseboard, module carrier, and front-panel boards (with on-board power and signal & power integrity), the electrical interfaces between modules, the PCIe host interface, and the scale-out fabric (leaf/TOR topology, oversubscription, intra-rack cabling, frontend and management network).
• Electrical closure: the end-to-end power architecture from the rack DC inlet to point-of-load (regulation, transient budget, protection coordination) and the end-to-end high-speed channel budgets across the full link.
• Integration & bring-up: hardware/firmware/software system bring-up and board/system validation.
• System reliability: the top-down system RAS (reliability, availability, serviceability) budget and its flowdown to module allocations.
• Org & program: build and lead the Systems team and own schedule and budget.
• Phase gates: EVT/DVT/PVT design sign-off.

• Shipped server/rack products at volume through an ODM/OEM/CM or a hyperscaler/DGX-class program, with design ownership.
• Fluent from L1–L10. From component/PCB through full server-node assembly and validation.
• Extensive direct line management experience and have run a hardware engineering organization from near-scratch to scale.
• Real NPI scars — owned EVT/DVT/PVT gates, spin decisions, and qualification.
• Board & system-electrical depth — layout direction, on-board power, SI/PI, high-speed interfaces (PCIe Gen6/7, Ethernet/OSFP), and validation.
• End-to-end channel & power closure — with owned link budgets for high-speed interfaces (PCIe Gen6/7, 800G+ Ethernet) and an end-to-end power architecture, not just board-level SI/PI.
• Operates well in a defined-interface organization — comfortable owning deep electrical authority while designing to interface definitions and product envelopes set by other teams.
• System-architecture ownership — has owned or led rack/tray/board architecture.
• 15+ years hardware development — BS/MS in EE/ME or equivalent track record.

• Rack/cluster integration (L11/L12) for AI training/inference deployments.
• Scale-out fabric/networking depth:
  Ethernet leaf-spine, OSFP, RDMA/RoCE.
• OCP experience: OAM/UBB and ORv3 rack power; contributor a plus.
• 0→1 startup experience or adjacency to…