Senior STA Engineer

Media Tek is a global fabless semiconductor industry leader, providing solutions from the edge to the cloud and powering over 2 billion connected devices every year. Established in 1997, our leading‑edge technologies keep the world connected and enhance everyday life. At the forefront of innovation, Media Tek drives advancements in transformative technologies such as AI, 5G/6G, and Wi‑Fi 8. Our high-performance, power‑efficient solutions form the foundation for a smarter, more connected world, enabling devices from smartphones, smart homes, and AI PCs to high‑performance computing, automotive, and AI data centers.

As a trusted partner to the world’s leading brands, we are committed to ensuring access to world‑class technology for everyone. Our dedication to accelerating AI underscores our mission to enrich the future of humanity.

Mobile CPUs push timing sign‑off to its limits — ultra‑wide voltage ranges, aggressive multi‑OPP targets, and sub‑2nm parasitics demand creative margin methodology. As a Senior STA Engineer you will be the timing authority for one or more CPU blocks, partnering with PD, RTL, and DFT teams to deliver clean sign‑off on Media Tek's next‑generation SoCs.

• Own block‑level STA sign‑off: constraint development, multi‑scenario regression, and timing closure
• Generate and drive timing and power ECOs through to resolution
• Partner with RTL and DFT teams to define accurate functional and test‑mode constraints
• Develop and champion advanced margining methodologies (AOCV/POCV) calibrated to silicon
• Analyze clock tree quality; guide physical implementation toward scalable, convergence‑friendly CTS
• Build custom sign‑off recipes for power recovery and timing closure in Tempus/Prime Time
• Deliver timing models (ETM, Hyperscale) and SDC/timing budgets for SoC integration
• Participate in Media Tek's worldwide STA forum; help define next‑generation margin methodologies

• 5+ years of STA experience on high‑performance CPU designs (≥ 2 GHz)
• Expert‑level understanding of multi‑scenario STA, SDC constraints, and timing exceptions
• Deep knowledge of OCV/AOCV/POCV margining and silicon correlation
• Multi‑OPP closure experience: resolving setup/hold conflicts across a wide voltage‑frequency range
• Familiarity with clock tree timing analysis and co‑optimization with physical design
• Experience developing custom timing closure and power‑recovery recipes in sign‑off tools
• Low‑power design knowledge including CPF/UPF multi‑voltage island methodology
• Proficiency with Cadence Tempus and/or Synopsys Prime Time
• Strong scripting skills in Tcl, Python, or Perl
• Advanced‑node tape‑out experience (7nm or below)
• Familiarity with physical design flows (synthesis, place‑and‑route, physical verification)
• IR drop analysis (static and dynamic)
• Salary range: $152,400 - $217,200 annually.
• Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual’s skills, experience and qualifications. In addition, Media Tek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, company paid holidays, paid time off (PTO), parental leave, 401K and more.
• Media Tek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.