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Senior Hardware Verification Engineer, UVM & Formal
Job in
Austin, Travis County, Texas, 78716, USA
Listed on 2026-07-19
Listing for:
River AI
Full Time
position Listed on 2026-07-19
Job specializations:
-
Engineering
Test Engineer
Job Description & How to Apply Below
River AI is seeking an exceptional design verification engineer to validate our high‑performance silicon and ensure functional correctness from architecture to tape‑out.
You will define verification strategies, build scalable UVM test benches in System Verilog, develop constrained‑random tests, apply formal methods, and use emulation platforms while collaborating across RTL, performance modeling and compiler teams.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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