Physical Design Engineer

Meet The Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco's core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry's only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you'll help shape Cisco's groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry.

RTL-to-GDSII implementation, including synthesis, hierarchical floor planning, place and route, static timing analysis, power integrity, and equivalence checks with a focus on performance and die size optimization.

Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.

Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.

Guide clock tree synthesis (CTS) strategies and provide actionable feedback to the implementation teams.

Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios.

Complete Timing ECO implementation using Tweaker/Primetime-based flows and contribute to automation for STA methodology.

Evaluate multiple timing methodologies/tools across different technologies and design types.

Master's degree or Bachelors degree in Electrical Engineering with work experience in Physical Design.

Experience with RTL design and logic blocks.

Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre.

Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.

Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.

Experience with Python, TCL, or Perl programming.