Member of Technical Staff, Hardware, RTL Design Engineer

At River, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, custom training infrastructure, next-generation UIs, and frontier deep learning research.

We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre‑training infrastructure behind today's frontier models.

We are looking for exceptional RTL design engineers to architect and implement high‑performance custom silicon. You will design and define the architecture, micro‑architecture, and implementation of complex AI accelerator and related SoC components on advanced foundry nodes. You will take ownership of large parts of the chip and be responsible for both functionality and PPA. You will be collaborating both up and down the stack with compiler and performance model teams, as well as with verification and physical designers.

• Architecture & Micro‑architecture:
  Create high‑level architectural specifications as well as detailed micro‑architectural designs for AI hardware subsystems.
• RTL Development:
  Design and implement complex logic using System Verilog, focusing on pipelines, throughput vs latency tradeoffs, and power‑efficient data paths.
• Physical Design Integration:
  Collaborate with the backend team on synthesis, floor planning, and power analysis. Drive and analyze static timing analysis (STA) to resolve timing violations and ensure the design meets target frequencies.
• Performance Integration:
  Collaborate with the compiler, performance modeling, and software team to identify bottlenecks in the micro‑architecture, architecture, ISA, kernels, and all the way up to the full system and end applications.

• Bachelor’s degree in Electrical Engineering or Computer Engineering, and 5+ years practical industry experience working with advanced process nodes (7nm or below).
• Deep hands‑on proficiency with industry‑standard RTL, synthesis, physical design, and timing tools (e.g., System Verilog, VCS/Verdi, Fusion Compiler, Prime Time).
• Expert knowledge in Computer Architecture of at least one style of chip, including SoCs, CPUs, GPUs, or AI accelerators.
• Proven track record of functional and performant silicon delivery, including experience in ECOs and reliable silicon at scale.
• A highly collaborative mindset to push boundaries and co‑design effectively with other engineers.

• Hands‑on experience in post‑Silicon bug fixing, firmware patching, and GPIO/I2C/SPI/UART low‑level debugging.
• Proficiency with C/C++/python and ISA assembly to understand and debug performance models and kernels.
• Experience with a high‑speed IO device such as PCIe, UCIe, or HBM/DDR memory controllers.
• Knowledge of NoC level communications, such as AXI, CHI, or any credit or valid/ready protocol.
• Logistics.

Location:

This role is based in Austin, Texas or Palo Alto, California.

• Compensation:
  Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD.
• Visa Sponsorship:
  We sponsor visas. We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.
• Benefits:
  River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.