Senior Principal Verification Engineer

Responsibilities

• Perform functional verification of CPU cores and related subsystems (coherency and cache controllers).
• Understand and interpret microarchitectural specifications to develop effective verification strategies.
• Develop and execute verification plans, including testbench creation and test case development.
• Write directed and constrained random test cases in System Verilog, C, and Assembly.
• Utilize UVM-based environments for coverage‑driven verification.
• Analyze coverage reports and assist in closing coverage gaps.
• Automate regression and verification flows using scripting languages such as Python, Perl, or Shell.
• Collaborate with senior engineers and architects to ensure design quality and performance.

• Bachelor’s degree in Electronics/Electrical/Computer Engineering.
• 15+ years of experience in design verification, preferably in CPU or SoC verification.
• Hands‑on experience with System Verilog, UVM, and constrained random verification.
• Familiarity with CPU architectures such as RISC‑V, ARM, or MIPS.
• Basic understanding of cache and coherency concepts.
• Strong scripting skills in Python, Perl, or Shell.