Design Verification and Emulation Manager

Overview

Design Verification and Emulation Manager in San Jose, CA or Pittsburgh, PA or Austin, TX. Efficient is developing the world’s most energy-efficient general-purpose computer processor. Our technology uses substantially less energy than state-of-the-art ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks, enabling AI/ML to run continuously on low-power devices. We are seeking a seasoned Design Verification & Emulation Manager to lead and scale our verification and emulation organization as part of our hardware engineering group.

This leadership role is responsible for silicon correctness and system-level readiness across multiple product lines. You will own the verification strategy from block-level to full-chip, drive emulation-based validation for early software enablement, and build a high-performing team of verification and emulation engineers.

This role combines deep technical expertise with strong people leadership and program execution skills, ideal for someone who works at the intersection of architecture, verification methodology, hardware-software integration, and team building. This is a unique opportunity to influence our products and processes as we move from early development toward market release and scaled volume production. Join our team and help shape the future of computing at the edge and beyond.

• Define end-to-end verification strategy from block-level through full-chip simulation, emulation, and prototyping
• Own UVM-based methodology
  , including constrained-random, coverage-driven closure, assertions, and formal verification adoption
• Drive emulation platform strategy — platform selection, capacity planning, compilation flows, and multi-project scheduling
• Enable system-level validation on emulation — processor boot, OS bring-up, firmware execution, and IO exercising
• Deliver pre-silicon platforms for early software development in partnership with firmware and software teams
• Establish hybrid simulation-emulation methodologies using transactor-based interfaces to maximize both environments
• Own functional coverage models and sign-off criteria
  , driving closure across simulation and emulation
• Lead debug and root cause analysis across simulation and emulation, driving cross-functional bug resolution
• Manage verification dashboards, bug tracking, and regression health to provide clear visibility to program leadership
• Build, mentor, and scale a high-performing team of verification and emulation engineers
• Drive verification schedules and risk mitigation aligned with chip program milestones and tapeout readiness
• Represent verification and emulation in tapeout readiness reviews and program-level decision forums
• Collaborate cross-functionally with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teams
• Manage emulation lab infrastructure
  , including hardware resources, licensing, and vendor relationships
• Evaluate and adopt new EDA tools and methodologies
  , including AI/ML-assisted verification techniques
• Define right DV mix for in-house vs outsourcing to 3rd party vendors
  . Coordinate 3rd party vendor resources towards achieving project goals.

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.
• Experience: 12+ years of progressive experience in ASIC/SoC design verification, including at least 3–5 years in a management or senior technical leadership role overseeing both verification and emulation functions.
• Verification Methodology: Deep expertise in UVM, constrained-random verification, functional coverage, assertions (SVA), and simulation-based debugging. Strong understanding of formal verification techniques.
• Emulation Platforms: Hands-on experience with at least one major emulation platform (Palladium, ZeBu, or Veloce) and familiarity with FPGA prototyping flows.
• Languages & Tools: Proficiency in System Verilog, Verilog, and C/C++ for testbench and reference model development. Experience with Python, Tcl, and scripting for flow automation.
• SoC Architecture: Solid understanding of…