ASIC Physical Design Principal Engineer

Your Impact

• RTL-to-GDSII implementation, including logic synthesis, hierarchical floor planning, place and route, static timing analysis, power integrity, and equivalence checks with a focus on power, performance, and die-size optimization.

• Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.

• Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.

• Guide clock tree synthesis (CTS) strategies and provide actionable feedback to the implementation teams.

• Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios.

• Complete functional and timing ECO implementation using industry-standard flows and contribute to automation for STA methodology.

• Evaluate multiple timing methodologies/tools across different technologies and design types.

• Bachelor's degree in engineering and 15+ years of ASIC related experience, master's degree in engineering and 12+ years of ASIC related experience, or PhD in engineering and 7+ years of ASIC related experience.

• Experience developing and driving methodologies in the area of power optimization and analysis.

• Experience with RTL2

GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.

• Experience working with EDA tools like Innovus, Primetime/Tempus, Redhawk/Voltus, and Calibre.

• Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.

• Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.

• Experience in fullchip floor-planning and power grid planning.

• Experience with custom clock (H-Tree or Mesh) at chip level.

• Experience with Python, TCL, or Perl programming.