Hardware Emulation Engineer

Employment Type:
Full-Time with L&T Technology Services (LTTS).

We are looking for a simulation acceleration candidate with the following qualifications:

Maintain simulation acceleration and emulation environments using Cadence Palladium and/or Synopsys ZeBu.

Port existing System Verilog/UVM test benches to acceleration/emulation platforms.

Partition verification environments between host and emulator while maintaining functional correctness and performance.

Optimize verification environments to reduce compile time and improve simulation performance.

Enable long-running regression tests and software-driven validation on acceleration platforms.

Integrate third-party VIPs and develop custom transactors where required.

Debug RTL, testbench, and acceleration-specific issues using waveform and emulator debug tools.

Collaborate with RTL designers, DV engineers, architects, firmware, and software teams to accelerate project milestones.