Server, Ddr Memory Training Validation Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next‑gen processors, enabling AI breakthroughs, or creating go‑to‑market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

In this role, you will be part of a dynamic team performing electrical validation of Datacenter Server SoC Post‑Silicon IO interface, in a way that is end to end customer focused, innovative, efficient and drives highest quality standards. It requires both pre and post Si engagement and close collaborations within and outside the team to ensure design and test content robustness, ultimately delivering highest quality products to customers.

In this role responsibilities will include but not be limited to work with senior engineers to:

• Improve process and throughput as it relates to memory training validation/debug.
• Understand FW Memory Interface Training algorithms in order to drive debug and validation methodologies specific to training.
• Understand the details of the DDRIO PHY design in order to facilitate more efficient debug strategies.
• Own, drive and debug Post‑Si electrical bugs and performance marginality with hardware/BIOS/Firmware/Operating System implementations and recommend solutions.
• Drive upstream requirements for pre‑silicon validation of Memory Interface Training to ensure high‑quality post‑silicon solution at first silicon.
• As part of a highly technical team, you will have the opportunity to innovate on and establish new test methodology, as well as new test development process improvements. Drive test optimizations to reduce test cost, enhance product quality, improve efficiency and accelerate stability.

• 4+ years of experience with:
• Hardware architecture, logic/circuit design and implementation
• Experience with DDR5, LPDDR5, JEDEC standards,
• Familiarity with programming / scripting language (C/C++, Python, Perl, ...)
• Familiarity with DFT, hardware testing methods and tools

• Experience with DDRIO Memory Training FW, PHY Logic and Circuit Validation and Debug, post‑silicon

• Candidate must possess a Bachelor’s degree in Electrical/Electronic Engineering or equivalent with desired experience in memory validation and characterization.

Austin, TX

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.