ASIC Design Verification Technical Leader - Acacia; hybrid

ASIC Design Verification Technical Lead Engineer

The ASIC Design Verification Technical Lead Engineer will be working on next-generation 100G-1.6T coherent optical communications products. This role is for a senior contributor & technical leader focused on verifying highly complex ASICs that are used in these next-generation systems. The role requires someone to demonstrate their experience applying sophisticated verification techniques to ASIC projects: ensuring design quality, leading sophisticated technical projects, developing process improvements for the team, and mentoring teammates on techniques, technology & methods for verification.

This role also requires significant communication skills (both written and verbal) to contribute to the ASIC projects, and working with other technical leaders in the engineering community.

In this role, you will need to operate independently with minimal direction in a fast-paced, dynamic, and highly technical environment, creating unique verification solutions and providing technical leadership to others on the team. A successful candidate will be highly self-motivated, collaborative, and passionate about delivering the most advanced high-speed optical products in the world. Knowledge of object-oriented verification methodologies is required.

In this role, you will:

• Lead and develop detailed and comprehensive test plans
• Lead and develop verification test benches
• Apply innovative verification techniques to complex designs
• Supervise the timely execution of test plans by the rest of the team
• Lead and assist with chip-level design tradeoffs by working with design engineers
• Participate in the review of design verification coding and coverage metrics
• Provide technical leadership & mentoring
• Work collaboratively with the team to develop & incorporate the latest test technologies & processes

• Bachelor's or Master's degree majoring in Computer Science, Computer Engineering, or Electronic or Electrical Engineering, with 12+ years of experience using the latest ASIC verification methodologies, tools, and scripting/programming languages
• Experience with System Verilog/UVM
• Experience with in house Verification Intellectual Property (VIP) development strategy

• Experience with C++ hybrid test benches
• Consistent track record of innovation that leads to quantifiable improvements
• Self-motivation and the ability to implement effectively without supervision
• Experience leading ASIC technical teams
• Knowledge of DSP algorithms and modulation techniques such as QAM
• Lab silicon validation experience
• Knowledge of Formal Verification methodologies and tools such as Jasper or VCFormal