Senior CPU Physical Design Engineer

Senior CPU Physical Design Engineer

As a Senior CPU Physical Design Engineer, you will play a critical role in delivering Intel's next-generation high-performance CPUs from concept through manufacturing. You will drive physical implementation and optimization of complex CPU designs, ensuring industry-leading performance, power efficiency, area optimization, and manufacturability. In this role, you will collaborate with architecture, logic design, circuit design, CAD, and validation teams to enable innovative computing solutions that power client, data center, and AI-driven products.

Your contributions will directly influence Intel's future technology roadmap and help shape the next generation of computing.

Join Intel's CPU Design team within the Silicon and Platform Engineering Group (SPE), where engineers develop industry-leading processor technologies that power billions of devices worldwide. Our team leverages advanced process technologies, innovative design methodologies, and cross‑functional collaboration to deliver world‑class CPU products and advance Intel's mission of creating world‑changing technology.

• Perform physical design implementation for custom CPU designs, transforming RTL into a design database ready for manufacturing.
• Execute all aspects of the physical design flow, including floor planning, synthesis, place and route, clock tree synthesis, static timing analysis, power/clock distribution, and noise analysis.
• Conduct verification and signoff processes, including formal equivalence verification, reliability verification, layout verification, and structural design checking.
• Collaborate closely with cross‑functional teams (logic, circuit, architecture, and design automation) to optimize CPU micro‑architectures for power, area, and frequency improvements.
• Build and refine physical design methodologies, enhancing flow automation and efficiency.
• Work with industry EDA vendors to improve design tools and enable high‑speed, low‑power synthesizable CPUs.
• Analyze design results and propose recommendations for optimizing current and future CPU micro‑architectures.

• Strong technical problem‑solving and analytical skills.
• Ownership and accountability for delivering quality results.
• Effective collaboration across diverse, global engineering teams.
• Strong written and verbal communication skills.
• Adaptability in a dynamic and fast‑paced development environment.
• A passion for continuous learning and technical innovation.

• Bachelor’s degree in Electrical/Computer Engineering, or a related field, with 6+ years of relevant experience. Or a Master’s degree in the same field with 4+ years of relevant experience. Or a PhD in the same field with 2+ years of relevant experience.
• Physical design EDA tools such as Synopsys Fusion Compiler, Cadence Genus/Innovus, or equivalent.
• Experience with scripting languages (e.g., TCL, Perl, Python) for tool automation and design exploration.
• Experience in backend design workflows, including constraints management, clock tree synthesis, static timing analysis, and layout verification.
• Completion of at least one tape‑out on advanced process nodes.
• Experience with RTL‑to‑GDS automation methodologies.
• AI/ML based automatic place‑and‑route methods for design efficiency and quality.

• Low‑power design techniques, multiple power domains (MPP/UPF), and power analysis methodologies.
• Digital design fundamentals, CMOS process technology, and CPU micro‑architecture.
• Experience collaborating with EDA vendors to refine tool capabilities.
• Multi‑vendor experience with thermal & power reduction techniques.
• Power/performance optimization trade‑offs in APR.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry.

It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $- USD. This role will require an on‑site presence. Job posting details (such as work model, location or time type) are subject to change. Position Type:
Experienced Hire.

Shift: Shift 1 (United States of America). Primary

Location:

US, Texas, Austin. Additional Locations: (open).