Senior Testchip SoC Physical Design Engineer; Integration & Methodology

About the Role

Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness. In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles.

You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.

• Develop layout design methodology for testchip development in next generation process nodes.
• Work closely with Process Integration, Yield, and QnR to define critical design features that need to be exercised in the early lead vehicle test chips.
• Establish, orchestrate, oversee, and maintain hierarchical layout design specifications for correct-by-construction integration.
• Build and execute tactical plans to converge hierarchical SoC layout design against aggressive schedule requirements by working closely with PDK teams.
• Drive all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools.
• Work with tool/flow owners and vendors for ongoing tool/methodology improvement.

• Strong interest in layout design at advanced technology nodes.
• Strong verbal and written communication skills.
• Ability to work well both autonomously and in an intensive, cooperative team environment.
• Coordinate between different stakeholders for testchip to arrive at execution commit for testchip.
• Motivation to continuously learn and drive for improved layout productivity and efficiency.

Work on cutting-edge semiconductor technologies that shape the future of computing. Collaborate with industry-leading experts across design and manufacturing. Opportunities for career growth and technical leadership. Contribute to innovations that impact global technology at scale.

• Master’s degree in electrical engineering or related field with a minimum of 5 years of experience in physical/layout design in advanced technology nodes.
• Experience with layout design tools such as Cadence Virtuoso Suite or Synopsys Custom Compiler, design rules and layout constraints in advanced semiconductor processes.
• Experience with floor planning, hierarchical design integration, and layout verification/debug.

• Experience in the definition of testchip/product design from concept to execution commit.
• Experience working with Foundry teams on negotiating features to exercise in design.
• Project management skills coordinating and tracking the entire design cycle from feature definition to final tape-in.
• Preferably previous related work experience in a semiconductor foundry.

• Job Type: Experienced Hire
• Shift: Shift 1 (United States of America)
• Primary
  
  Location:
  
  US, Oregon, Hillsboro
• Additional Locations: US, California, Santa Clara
  • US, Texas, Austin
• Annual Salary Range (US): $ – $ USD
• Work Model:
  Eligible for hybrid work allowing employees to split time between on-site and off-site. (Details subject to change.)

We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation. See Intel Benefits for more details.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.