Data Center SoC Power & Limits Architect

Company

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > ASICS Engineering

The Data Center Power & Limits Architect will define and drive next-generation power management, thermal, and system limits architecture for large-scale compute platforms (SOC, servers, racks, and cluster-level deployments).

With AI/HPC workloads pushing infrastructure to electrical and thermal limits, this role is responsible for enabling maximum sustained performance within constrained power, cooling, and reliability envelopes by architecting end-to-end power and limits systems across silicon, platform, and data center infrastructure.

• Power & Limits Architecture Definition
  • Define holistic power, thermal, and electrical limits architecture across silicon, board, system, rack, and cluster levels
  • Architect power budgeting, allocation, and enforcement mechanisms across CPU, GPU, memory, accelerators, and I/O
  • Develop strategies to maximize performance under datacenter-level constraints (rack power caps, cooling limits, PUE targets)
• Dynamic Control & Optimization
  • Architect advanced dynamic power control systems (e.g., DVFS/DCVS, AVS-like systems) for fast transient response
  • Design closed-loop control systems using telemetry and feedback to optimize performance vs. constraints
  • Develop proactive and reactive limit management (thermal throttling, power capping, workload shaping)
• Telemetry & System Integration
  • Define requirements and interfaces for telemetry infrastructure (sensors, BMC, firmware, system SW)
  • Enable real-time monitoring and decision making across system layers
  • Ensure integration with platform controllers (e.g., BMC/EC, rack management, orchestration layers)
• Cross-Layer Co-Design
  • Collaborate with:
    Silicon/SoC architects (power islands, regulators, sensors), Platform teams (VRs, PDN, cooling), Software/firmware teams (power management algorithms), Data center infrastructure teams (rack-level optimization)
  • Define hardware/software partitioning for limits enforcement with minimal overhead
• Modeling, Simulation & Validation
  • Develop system-level models (MATLAB/Simulink, architectural simulators) to:
    Predict performance vs. power/thermal constraints
  • Evaluate algorithms and architecture trade-offs
  • Perform workload-driven analysis to validate architecture decisions
• Innovation & Future Architecture
  • Drive innovations in:
    Power delivery efficiency, Thermal-aware scheduling, AI workload-aware limits, Rack/cluster-level power orchestration
  • Define next-generation architectures to support scaling AI/HPC performance under constrained infrastructure

• 10+ years of experience in power architecture, system architecture, or related domains
• Deep expertise in:
  • Power management systems and limits control
  • Thermal and electrical constraints in high-performance systems
  • DVFS/DCVS, power capping, and control systems
• Strong understanding of:
  • Data center/server architecture (CPU/GPU/accelerators, memory systems)
  • Power delivery networks (VRs, PDN, rack power distribution)
  • Telemetry, sensors, and system monitoring
• Experience with modeling and analysis tools (e.g., MATLAB, Python)

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

$ - $

Salary is one component of total compensation itionally, we offer a competitive annual discretionary bonus program and opportunity for annual RSU grants. We offer a highly competitive benefits package designed to support your success at work, at home, and at play.

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.