Staff Digital Design Engineer – SOC Low Power, Clocking & Integration

Staff Digital Design Engineer - SOC Low Power, Clocking & Integration page is loaded## Staff Digital Design Engineer - SOC Low Power, Clocking & Integration locations:
Austin time type:
Full time posted on:
Posted 2 Days Agojob requisition  Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets.

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** Staff Digital Design Engineer - SOC Low Power, Clocking & Integration Austin, TX
**** Meet the Team
** The IoT Digital Design team is a state-of-the-art IC design team focused on producing world class Wireless MCU SoCs. The architecture specifications, design, verification, emulation, and implementation of the Wireless MCU SoCs are all the responsibilities of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, advanced power management, and best in class radios to support a wide range of wireless IoT applications and standards.

We strive to provide advanced technology solutions through innovation in custom RISC-V Cores and AI/ML components.
** Responsibilities
* * The Role as a Staff Digital Design Engineer, you will develop world class, highly integrated, low power, System on a Chip device to serve the IoT wireless market. Responsibilities include the following:
* Develop complex SOC/chip Architectures with multiple processors, digital and mixed signal subsystems, multiple power, and clock domains with a goal towards optimizing power for specific customer scenarios.
* Define and implement SoC-level low-power architecture, including power domains, retention, isolation, level shifters, and power sequencing.
* Develop and integrate UPF/CPF-based power intent across subsystem and SoC hierarchies.
* Collaborate with architects to define power management strategies that meet performance, power, and area targets.
* Design and integrate clocking infrastructure, including clock generation, clock distribution, clock gating, clock muxing, reset architectures, and clock monitoring mechanisms.
* Drive RTL design and integration of power management controllers, clock controllers, reset controllers, and related infrastructure IPs.
* Prepare and hold architecture, design, and verification reviews with technical staff throughout project lifecycle
* Analyze and debug low-power and clocking issues identified during simulation, emulation, synthesis, and silicon bring-up.
* Architect and integrate SoC interconnects and bus fabrics, including AXI, AHB, APB, and other on-chip communication protocols.
* Lead small teams of design engineers to architect, design and verify digital subsystems.
* Drive subsystem and SoC integration activities, ensuring seamless connectivity between processors, memories, peripherals, accelerators, and third-party IPs.
* Drive RTL development and integration of infrastructure IPs, including clock controllers, reset controllers, power management controllers, DMA engines, and bus fabric components.
* Analyze and debug integration, clocking, power, CDC/RDC, and protocol-related issues throughout the development cycle.
* Validation/bring-up of designs on silicon, providing support to cross-functional teams
** Skills You Will Need
** BS/MS in Electrical Engineering
* 10-20 years of professional experience in digital CMOS IC design
** Minimum Qualifications
*** Demonstrated ability to lead small teams designing complex digital subsystems
* Strong RTL design expertise using Verilog/System Verilog.
* Solid understanding of SoC clocking architectures, clock domain crossing (CDC), reset domain crossing (RDC), synchronization techniques, and timing considerations.
* Extensive experience with low-power design methodologies, including UPF, power gating, retention, isolation, level shifting, and power-aware verification.
* Strong experience with industry-standard on-chip bus protocols such as AXI, AHB, APB, and related interconnect architectures.
* Experience integrating complex subsystems, processor clusters, memory subsystems, and third-party IPs into large SoCs.
* Knowledge of embedded processor systems and C coding
* Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis tools
* Experience with logic synthesis and timing constraints
* Experience in working with backend team to optimize design for power performance and area.
* Experience in working with analog and mixed signal designs, to support design integration and verification of these subsystems in SOC.
* Experience with scripting and automation. Knowledge of…