RF​/Analog IC Layout Engineer

RF/Analog IC Layout Engineer

Work location:

SF Bay Area, San Diego, Austin, TX Onsite Contract

Job Description:

Custom RF/Analog Layout Engineer

You will work along our layout engineers and RF designers to build detailed transistor-level layout of RF and analog circuit blocks including bandgap/bias/LDO, ADC/DAC, baseband filters, modulators, power amplifiers, PLL, LO generation, LNA, and mixer. You will also be responsible to provide high quality layout to pass our verification flows including extraction, DRC, LVS, and DFM checking. Layout quality will be reviewed for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.

Collaborate closely with Layout Engineers and RF Designers to create detailed, transistor-level layouts for cutting-edge RF and analog circuit blocks. You will be instrumental in ensuring the highest quality layout that successfully passes rigorous industry-standard verification flows.

Key Responsibilities:

• Develop detailed transistor-level layouts for complex RF and analog circuit blocks, including:
  Bandgap/Bias/LDO, ADC/DAC, baseband filters, modulators, power amplifiers, PLL, LO generation, LNA, and mixer.
• Ensure all layouts meet stringent verification flow standards, including:
  Extraction, DRC (Design Rule Checking), LVS (Layout Versus Schematic), DFM (Design for Manufacturing) checking.
• Conduct thorough layout quality reviews focusing on:
  Power and ground routing integrity and electromigration compliance, critical signal path verification and optimization, precision in differential and IQ matching, mitigation of signal coupling effects.

Mandatory skills and skill proficiencies required for this position:

• Proven experience with FinFET technology.
• Demonstrated expertise in custom RF/analog layout for analog or RF transceivers.
• Extensive, practical knowledge of deep sub-micron CMOS processes.
• High proficiency in interpreting results from verification tools such as CALIBRE DRC, ERC, and LVS.
• Familiarity and working knowledge of CADENCE layout tools.

Optional skills and skill proficiencies for this position:

• Strong understanding and application of advanced layout techniques for: precise device matching, minimizing parasitics, effective RF shielding, optimized high-frequency routing.
• Solid technical grasp of effects like RC delay, electromigration, and coupling.
• Knowledgeable about critical process-related layout structures, including guard rings, DNW (Deep N-Well), PN junctions, and advanced process effects (e.g., LOD, WPE).
• Excellent communication skills and proven ability to effectively collaborate with designers and other layout engineers.