Custom Timing and Verification CAD Engineer

Apple's custom silicon is among the most sophisticated in the world - and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom Timing CAD team builds and owns the flows, tools, and methodologies that make that verification possible. We are looking for an entry-level engineer who is eager to learn, technically curious, and excited to work at the intersection of circuit design and CAD engineering.

Description

In this role, you will support and develop flows for two of the most critical sign-off disciplines in custom IC design - transistor-level timing verification using Nano Time and formal verification using ESP. You will partner closely with analog and digital designers across multiple programs and technology nodes, helping them set up flows, debug issues, and achieve clean sign-off. The work you do will directly shape the quality and schedule of Apple's most advanced chips.

Minimum Qualifications

Minimum of BS degree in Electrical Engineering, Computer Engineering, Computer Science, or related field + 10 years relevant industry experience

Strong programming or scripting experience in Perl, Python, TCL, or similar language

Solid understanding of digital or custom IC design at transistor level and static timing analysis

Preferred Qualifications

Hands-on experience with transistor-level timing and formal verification tools such as Nano Time, ESP, Prime Time, or HSPICE, including flow ownership and methodology development

In-depth knowledge of dynamic logic, memory arrays, or mixed-signal circuit techniques, and ability to debug complex timing and verification issues independently

Experience with SPICE netlists, device models, and parasitic extraction formats such as DSPF or SPF in the context of timing sign-off

Experience with formal verification methodologies and System Verilog RTL, including RTL-to-schematic equivalence checking

Track record of driving cross-functional collaboration with design, layout, and EDA vendor teams to resolve tool and methodology issues

Experience developing or contributing to organization-wide CAD methodology documentation and best practices

Familiarity with AI/ML-driven CAD workflows and interest in applying GenAI techniques to flow automation and timing analysis

Strong communicator with the ability to present technical work clearly to both peers and management, and drive issues to resolution across teams