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Senior DFT Engineers
Job in
Austin, Travis County, Texas, 78716, USA
Listed on 2026-09-01
Listing for:
Digicomm Semiconductor INC
Full Time
position Listed on 2026-09-01
Job specializations:
-
Engineering
Test Engineer
Job Description & How to Apply Below
- Run formal verification between synthesized netlist and post DFT netlist.
- Generate DFT constraints for backend and Primetime.
- Provide BE team with post DFT netlist and associated constraints.
- Validation plan and test development.
- Generate ATPG Test Patterns.
- Block level and soc level patten generation.
- Monitor test coverage and pattern counts.
- Run ATPG and pattern verification on DFT inserted netlist
- MBIST pattern RTL and gate level validation.
- Run full MBIST, scan pattern generation and verification (both pre and post layout netlist)
- After chip top netlist is available, all block MBIST, scan pattern generation and verification should be run from top level.
Position Requirements
10+ Years
work experience
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