Physical Design Engineer

Qualcomm seeks a Senior Physical Design Engineer to drive implementation of high-performance wireless and 5G SoC blocks from RTL to GDSII. You will own floor planning, place-and-route, CTS, timing closure, power and area optimization for advanced process nodes. Collaborate with architecture, RTL, DFT, and verification teams to meet aggressive performance and power targets. Responsibilities include static timing analysis, physical verification, ECO implementation, scripting for flow automation, and working with foundries and EDA vendors.

This role suits engineers who thrive in an innovative, fast-paced, globally collaborative environment.

Responsibilities

• Own RTL-to-GDSII physical implementation for complex So
• C/IP blocks
• Perform floor planning, place-and-route, and clock-tree synthesis
• Drive timing closure using static timing analysis and optimization techniques
• Optimize for power, performance, and area across advanced process nodes
• Run physical verification, DRC/LVS, and resolve signoff issues
• Implement ECOs to address functional, timing, and physical issues
• Collaborate with architecture, RTL, DFT, and verification teams
• Develop and maintain scripts to automate physical design flows
• Interface with foundries and EDA vendors to resolve tool and PDK issues
• Contribute to methodology improvements and best practices

Required Skills

• Physical design (RTL-to-GDSII)
• Floor planning
• Place-and-route
• Clock-tree synthesis (CTS)
• Static timing analysis (STA)
• Power, performance, area (PPA) optimization
• DRC/LVS and physical signoff
• ECO implementation
• Scripting (Python, TCL, Perl)
• Experience with advanced process nodes (7nm or below)