Security IP Verification Engineer

Job Description:

Our Arm Security IP Team is seeking creative and enthusiastic Design Verification Engineers to join our team. We have exciting opportunities in our team for verification engineers with demonstrated expertise in Security Design Verification including Cryptography, Key Management, Embedded Microprocessor Systems, Hardware Root of Trust, and Secure Boot. You will contribute to the design specification, test planning, testbench development, verification, and productization of Security IP for pioneering SoC designs.

This is a fantastic opportunity to work with a groundbreaking team specializing in security, power, and performance! Our team offers great opportunity for professional growth and technical advancement. Are you ready to make an impact?

As a creative problem solving Security and Embedded Processor Verification Engineer, you will be part of a team that will define and realize the Hardware Security IP and Subsystem. We will develop the test plans, test benches, verification models, and test strategies. We will partner with the design team for functional sign off and comprehensive coverage, as well as power and performance optimization.

Our key responsibilities include will include crafting test plans, developing UVM, System Verilog/Verilog, and C test benches and tests, and debugging of test failures and issues. On top of Security IP verification, our team contributes to development and enhancement of the design and verification methodologies shared across Arm. You will mentor members of the team as needed to enable the successful completion of projects, plus balance other opportunities such as working with Project Management on initiatives, plans, and schedules.

In addition to bringing your accomplishment of either Bachelors or Master’s degree in Computer Science or Electrical/Computer Engineering (or similar field) over 5+ years of experience working in design or verification of sophisticated IP, embedded compute subsystems, or SoCs, you will need:

• Solid understanding of digital hardware Verilog HDL and Verification strategies including, System Verilog UVM, C, Formal, and Hardware/Firmware co-verification.
• Verification experience in Security Hardware, Embedded Processor Systems, Applied Cryptography, Secure Boot, and Key Management.
• Proven experience in complex digital IP architecture and development including multi-clock domain designs, AXI/AHB protocols, multi-power domains, and reset architectures.
• Experience with Perl, Python, Tcl, or other scripting languages.
• Experience with ARM-based designs and/or ARM System Architectures.
• Experience verifying IP or SoC projects or systems including embedded microprocessors. Preference for candidates with experience in firmware/hardware co-verification or formal verification.
• Low-level programming experience including C and Assembler. Experience with firmware debug and tarmac logging.

• Experience with Arm-based designs and/or ARM System Architectures
• Clock domain crossing verification
• Power aware verification

Please note that no relocation package is available for this role. #LI-KC1

$161,500-$218,500 per year

We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process.

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email  To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation.

Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility.…