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Senior STA & Timing Closure Engineer - ASIC​/SoC; -Level

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Sivaltech
Full Time position
Listed on 2026-09-09
Job specializations:
  • Engineering
    Electronics Engineer, Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 120000 - 180000 USD Yearly USD 120000.00 180000.00 YEAR
Job Description & How to Apply Below
Position: Senior STA & Timing Closure Engineer - ASIC/SoC (Top-Level)

Sivaltech is seeking an experienced ASIC/SoC timing closure specialist for top-level signoff in a cutting-edge environment. Your expertise will drive timing closure, signoff accuracy, and ECO validation for complex SoCs in a fast-paced semiconductor team.

• Proficient in Prime Time/Tempus, CMA, and signoff methodologies.
• Strong scripting in Tcl and Python to automate flows.
• Collaboration with design, verification, and tapeout teams for successful silicon.

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Position Requirements
10+ Years work experience
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