Principal Product Engineer, HPC Products

Principal Product Engineer

Arm is seeking a Principal Product Engineer to lead productization of next-generation high-performance compute (HPC) silicon from pre-silicon readiness through bring-up, qualification, production ramp and HVM. This senior technical role owns cross-functional execution across silicon characterization, performance/power correlation, High-Speed I/O (HSIO), manufacturing test/SLT, yield, reliability and advanced packaging. The successful candidate combines deep silicon expertise with strong product ownership and data-driven execution.

• Own end-to-end Product Engineering execution for complex HPC products from product definition through HVM, driving readiness, risk mitigation and technical closure across major milestones.
• Partner with Architecture, Design, DFT/DFX, Validation, Software, Test and Product Management to define productization requirements, silicon observability, characterization plans and manufacturing readiness.
• Lead first-silicon bring-up and PVTF characterization, including Vmin/Fmax, voltage-frequency behavior, leakage, dynamic power, thermal behavior, silicon distributions and production guard bands.
• Drive performance and power correlation from pre-silicon models through silicon and system measurements; translate findings into product limits, binning, fusing and optimized operating points.
• Own HSIO productization and characterization strategy for interfaces such as PCIe/CXL, DDR/LPDDR/HBM, Ethernet/Ser Des and die-to-die interconnects, including margining, BER, jitter, eye margin, training/equalization and system-level debug.
• Drive correlation across ATE, bench, SLT and representative platforms, including interactions among silicon, PHY, package, PCB, SI/PI, power delivery, thermal conditions and firmware/software.
• Own manufacturing test and SLT strategy across wafer sort, final test and system-level environments, balancing coverage, outgoing quality, test time and cost.
• Drive yield learning, product limits, qualification, reliability and failure analysis from first silicon through mature HVM; partner with foundry, OSAT and manufacturing/test suppliers on root cause and corrective actions.
• Support advanced 2.5D/3D and chiplet-based productization and establish data-driven product-health metrics for yield, performance, power, HSIO margin, quality and manufacturing stability.
• Provide senior cross-functional technical leadership, communicate complex issues to engineering and leadership teams, and mentor engineers on Product Engineering methodologies and best practices.

• Bachelor's, Master's or Ph.D. in Electrical Engineering, Computer Engineering or a related technical discipline, with typically 12+ years of semiconductor industry experience.
• Demonstrated experience bringing multiple complex CPU, GPU, accelerator or SoC products from pre-silicon through production/HVM, preferably on advanced process nodes.
• Deep knowledge of silicon power, performance, voltage, frequency and temperature relationships; hands-on experience with PVTF, Vmin/Fmax, silicon variation and design-to-silicon correlation.
• Strong understanding of semiconductor manufacturing flow, DFT/DFX, wafer sort, final test, SLT, qualification, binning, fusing, guard banding and HVM yield optimization.
• Working knowledge of HSIO productization, characterization and debug, with experience in one or more of PCIe/CXL, DDR/LPDDR/HBM, Ethernet/Ser Des or die-to-die interfaces.
• Ability to analyze large silicon datasets and drive structured root-cause decisions; experience with analytics/scripting tools such as JMP, Silicon.da/Optimal+ or equivalent is valuable.
• Proven ability to lead complex cross-functional technical programs without direct organizational authority, with strong communication and problem-solving skills.

• Direct experience with HPC, server-class CPUs, GPUs or AI/ML accelerators, particularly high-core-count/high-power products.
• Experience with 2.5D/3
  
  DIC, chiplet architectures, advanced packaging, power delivery and thermal constraints.
• Hands-on HSIO margining/system debug and experience establishing HSIO production screens…