Principal Design Verification Engineer – CPU Subsystem

Principal Design Verification Engineer

SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for a high-performance CPU subsystem spanning both out-of-order CPU core development and cache-coherent interconnect/subsystem behavior.

• Lead verification strategy and execution for high-performance CPU subsystem development, covering OoO core microarchitecture and coherent interconnect/subsystem behavior.
• Own verification planning, execution, debug, coverage analysis, and closure from block level through subsystem integration and signoff.
• Define verification strategies for complex CPU behaviors including branch prediction, instruction fetch, issue/dispatch behavior, pipeline interactions, load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness.
• Define verification strategy and closure criteria for coherent traffic, protocol correctness, ordering rules, back pressure, buffering behavior, arbitration, QoS, and error handling across cache-coherent interconnect paths.
• Drive verification across interface boundaries, bridges, and protocol adaptation paths, including conversion, buffering, and related subsystem-level data movement behavior.
• Develop high-value checkers, scoreboards, assertions, stimulus strategies, and coverage models to expose corner cases and improve bug-finding efficiency.
• Apply the right verification method for the problem, using simulation, formal techniques, and emulation to improve quality and accelerate turnaround.
• Partner with architects and designers from early feature-definition stages to review specifications, identify ambiguity, and improve designs from a verification and debugability perspective.
• Drive efficient failure analysis and root‑cause debug across specification, RTL, test content, and verification infrastructure.
• Mentor engineers, influence team-wide methodology, and shape reusable verification approaches that benefit future generations of high-performance CPU subsystems.

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU/core or SoC functional verification, with depth appropriate for a Principal / T6 role.
• Direct experience with out-of-order core verification and strong understanding of CPU microarchitecture.
• Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, and verification of ordering and flow‑control semantics.
• Deep expertise in one or more CPU areas such as Frontend, Midcore, Load–Store Unit, memory ordering/consistency, or hardware prefetch verification.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and ability to translate architectural intent into effective verification strategy and execution.
• Strong software development, scripting, and automation skills for building scalable DV infrastructure and workflows.

• Experience spanning both high-performance CPU core verification and coherent interconnect, cache, or memory-subsystem verification in large SoCs.
• Experience with subsystem integration, bridge-heavy designs, or protocol interactions across multiple interfaces.
• Experience using formal verification for bounded, interface-heavy, or high-risk microarchitectural problems.
• Experience using emulation to accelerate verification and improve turnaround on large CPU and subsystem verification workloads.
• Experience collaborating effectively with performance, compiler, software, formal, and system verification teams to close gaps from multiple perspectives.
• Demonstrated…