AMD Test Engineer; Infrastructure/Speed I/O Specialty
Listed on 2026-09-12
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Engineering
Test Engineer, Hardware Engineer
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AMD is seeking an experienced Test Engineer to lead the architecture, development, and integration of wafer-sort test infrastructure on Advantest V93000 platforms using Smar Test 8. You will contribute to AMD’s common Base Test Program and Test Shell while leading or co-leading test enablement for high-speed I/O and die-to-die interfaces.
This role combines hands-on test program development with technical leadership across Product Engineering, Design for Test, Test Engineering, Yield Engineering, Test Hardware, and Manufacturing. Your work will improve test quality, yield, test time, scalability, and release readiness for modern microprocessor and chiplet-based products.
THE PERSON:You are a hands-on ATE Test Engineer with deep experience developing and debugging test programs on Advantest V93000 platforms. You understand how silicon, test software, tester hardware, probe hardware, patterns, timing, and manufacturing processes interact; and you are comfortable leading complex debug efforts across these areas.
You bring strong technical judgment, disciplined software-development practices, and the ability to influence infrastructure strategy across products and teams. You communicate effectively with geographically distributed engineering and manufacturing partners, mentor other engineers, and use AI-enabled tools and workflows to improve engineering productivity.
KEY RESPONSIBILITIES:Contribute to the architecture, development, and integration of the wafer-sort Base Test Program and common Test Shell, including reusable services, configurations, test flows, diagnostics, data collection, release controls, and product-integration interfaces.
Lead Smar Test 8 and Advantest V9300 test program infrastructure development, debug, validation, release readiness, and production support.
Define scalable architecture and coding practices that enable reuse across products, derivatives, silicon revisions, test insertions, and manufacturing sites.
Lead or co-lead wafer-sort test strategy, first-silicon bring-up, characterization, margining, screening, diagnostics, and failure isolation for high-speed I/O and die-to-die interfaces.
Integrate patterns, vectors, timing, levels, test methods, device configurations, binning, data collection, and debug capabilities into the common test program.
Debug complex interactions across silicon, test software, tester hardware, probe hardware, patterns, timing, and manufacturing processes.
Partner with Design, Design for Test, Product Engineering, Yield Engineering, Test Hardware, and Manufacturing teams to identify coverage gaps, improve testability, and resolve product and production risks.
Drive improvements in test quality, manufacturing yield, test time, maintainability, correlation, and release discipline.
Lead technical reviews, document architectural decisions, mentor engineers, and influence infrastructure direction across project and functional boundaries.
Support geographically distributed engineering teams, outsourced semiconductor assembly and test partners, and equipment vendors throughout development and high-volume manufacturing.
Extensive Advantest V93000 test program development and debug experience.
Smar…
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