Principal System Debug Engineer

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As a Principal System Debug Engineer, you will lead the system-level debug of our advanced microprocessors within complex customer applications and system design environments. You will act as the critical bridge between our internal silicon/software engineering teams and our top-tier OEM, ODM, and Hyperscaler customers.

This is a highly visible, cross-functional leadership role that requires deep technical expertise in CPU architecture, high-speed I/O interfaces, firmware/BIOS, system software, drivers, OS/kernels and software stacks, and platform hardware design, signal integrity, power integrity. You will drive the investigation, root-cause analysis, and resolution of the most complex, system-level CPU issues in the context of new system bring-up and customer applications and platform level debug

You are a subject matter expert and strong technical contributor with strong processor architecture, hardware and software expertise, and extensive system level debug experience. You excel as part of a team where technical leadership, customer engagement, communication and team skills are highly valued.

• Technical Leadership & Debug:
  Lead
  the triage, investigation, and root-cause analysis of complex system-level issues involving CPU silicon, platform hardware, firmware, drivers and OS/hypervisor interactions in customer environments.
• System Bring-Up:
  Drive
  early platform bring-up activities for next-generation CPUs, both in internal labs and on-site at customer facilities, ensuring rapid time-to-market.
• Customer Engagement:
  Serve
  as the primary technical liaison for strategic customers. Guide customer engineering teams through platform design, debug methodologies, and issue resolution.
• Cross-Functional Collaboration:
  Partner
  closely with internal Silicon Design, Architecture, Firmware (BIOS/UEFI/BMC), OS/Kernel, and Validation teams to drive systemic fixes and influence future CPU architectures based on customer feedback.
• Debug Methodology & Tooling:
  Architect
  and develop advanced debug methodologies, scripts, and tools to accelerate issue isolation across the hardware/software boundary.
• Escalation Management:
  Act
  as the technical task force leader during critical customer escalations, providing clear executive updates and driving technical action plans under tight deadlines.

• CPU Architecture:
  Deep
  , foundational knowledge of modern CPU architectures (x86 mandatory), including pipelines, cache coherency, memory controllers, and power management (C-states, P-states). RAS features, MCA (Machine Check Architecture), SoC and platform security features, RoT (root-of-trust).
• I/O & Interconnects:
  Extensive
  expertise in the architecture and protocol-level debug of high-speed I/O interfaces, including PCIe (Gen 4/5/6), CXL, DDR4/DDR5, Ethernet, USB, and low-speed buses (I2C, SPI, I3C, eSPI).
• Firmware & Software Stacks:
  Strong
  understanding of the full system software stack, including BIOS/UEFI, BMC/IPMI, Linux/Windows kernel internals, device drivers, and hypervisors (KVM, VMware, Hyper-V).
• Platform Design:
  Solid
  grasp of system-level hardware design, including board schematics, PCB layout, power delivery networks (VRMs), clocking,…