Graphics IP RAS Engineer

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As an AMD Graphics IP (GXIP) RAS Engineer, you will work at the intersection of GPU and MI accelerator architecture and Reliability, Availability, and Serviceability (RAS) requirements. This role is designed for a strong mid‑level engineer who is interested in system reliability and wants to grow into a RAS architecture role.

You will work closely with experienced GFXIP, AI, and RAS architects to help design, analyze, and improve RAS features for next‑generation AMD products across data center, client, and automotive markets. Through hands‑on participation and mentorship, you will build expertise in RAS concepts, architectural tradeoffs, and hardware reliability.

This role provides exposure to real production silicon, cross‑functional collaboration, and increasing technical ownership as your RAS experience grows.

You are a solid engineer with a strong technical foundation who is interested in system robustness and reliability. You are comfortable working across disciplines, asking questions, and learning from more experienced engineers. You communicate clearly, value collaboration, and are motivated to develop deeper architectural skills.

You do not need to be a RAS expert on day one—curiosity, fundamentals, and growth mindset matter more than prior RAS ownership.

• Contribute to the definition and development of RAS features and capabilities for next‑generation GFXIP deployments.
• Assist in writing and reviewing architectural specifications related to RAS features.
• Work with senior RAS and GFXIP architects to learn and apply reliability concepts, including error detection, containment, recovery, and reporting.
• Help analyze and understand reliability metrics such as FIT, DPPM, MTBF, and MT , and how they trade off against performance, power, area (PPA), and security.
• Support hardware design teams in evaluating RAS protection and coverage, and in identifying gaps or improvement opportunities.
• Collaborate across SoC, RAS, and business teams to ensure RAS requirements are understood and correctly implemented.
• Experience designing, analyzing, or implementing hardware or system features in VLSI‑based designs.
• Solid understanding of digital logic, computer architecture, and hardware design fundamentals.
• Ability to read and reason about specifications, RTL, and architectural documentation.
• Good communication skills and ability to work in cross‑functional engineering teams.

• Experience in computer architecture required.
• Exposure to or interest in reliability, fault tolerance, or system‑level robustness.
• Familiarity with RAS‑related concepts or mechanisms such as:
  Parity and ECC, Watchdog timers, Heartbeat monitors, Deferred or recoverable error handling
• Background in GPU architecture.
• Experience with RTL design a plus
• Interest in understanding failure rates and figures of merit.
• Exposure to AI/ML accelerator architectures and AI compute environments.
• Interest in reliability challenges in large‑scale AI systems and accelerator deployments.