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SoC Design Verification Engineer

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Inspire Semiconductor
Full Time position
Listed on 2026-09-25
Job specializations:
  • Engineering
    Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 120000 - 180000 USD Yearly USD 120000.00 180000.00 YEAR
Job Description & How to Apply Below

About Us:

At Inspire Semi ,we'renot just building a chip;we'rerevolutionizing high-performance computing. Our groundbreaking architecture packsthousands of 64-bit CPU coresonto a single chip, all tightly integrated with a high-performance interconnect.

We'redriven by a mission to make high-performance computing more accessible and energy-efficient, with a developer-friendly programming model. Ready to make a real impact? Join our passionate team!

Why Join Inspire Semi ?
  • Make an Impact:Your work will directly contribute to building a high-performancecomputeaccelerator for scientific, AI, and other applications.
  • Rewarding Compensation:We offer competitive salaries, benefits, and equity.
  • Flexibility:Benefit from ahybrid work environment in our Austin offices, with exceptional candidates considered forfully remote work.
  • Grow With Us:Contribute to the development and improvement of verification methodologies, tools, and automation scripts.
The Opportunity:

We are looking for aSoC Design Verification Engineertosupportthe complete verification of our innovative System-on-Chip (SoC). This critical role encompasses ourRISC-V core, network, and 3rd-party peripheral IP integrations. You willbe responsible for developing comprehensive verification plans, building test benches, and ensuring the highest level of design quality and functional correctness before tape-out.

What You'll Do:
  • Develop and executeverification plansfor complex SoC digital designs.
  • Create and maintainUVM/System Verilogbased testbenchesand environments.
  • Write, debug, and executeconstrained-randomand directed test cases.
  • ImplementRISC-V ISA compliance tests.
  • Perform functional coverage analysis andclose coverage gaps.
  • Perform regression runs,analyze failures, and drive bug closure.
  • Connect simulations to real user interfaces, stimulus generators, and checkers.
  • Collaborate closely with RTL design engineers, architects, and software teams.
  • Contribute to the development and improvement of verification methodologies and automation scripts.
  • Perform preliminary debug of discovered issues.
What You Bring:
  • ABachelor's or Master's degreein Electrical, Electronics, or Computer Engineering (or related field).
  • 5+ yearsof hands-on experience in ASIC/SoC design verification.
  • Strongproficiencyin System Verilog , UVM, and simulation tools (e.g.,Xcelium).
  • Solid understandingofdigital design fundamentals, RTL design, and synthesis flow.
  • Experience with functional coverage, assertions, andscoreboarding.
  • Strong scripting and programming skills(Python, Perl, TCL, C/C++).
  • Knowledge of common bus protocols (AXI, AHB, PCIe, DDR4/5, etc.).
  • Working knowledge of version control and continuous integration tools (e.g.,Git, Jenkins, Jira, and Confluence).
  • Solid debugging skills, analytical thinking, and attention to detail.
Bonus Points:
  • Experience with Formalverification(Conformal LEC).
  • Hands-on experience withemulation systems(Zebu, Palladium) orFPGA prototypes.
  • Experience with Cadence EDA tools.

Ifyou'reexcited about pushing the boundaries of computing and working on truly innovative technology in a rewarding environment,we'dlove to hear from you!

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