ASIC Physical Design Engineer

The application window is expected to close on: 10/08/2026

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry.

As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips. You will:

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 2nm).
• Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies using tools like Prime Closure/Prime Time.
• Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.
• Evaluate and implement new timing methodologies; provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

• Bachelors degree in Electrical Engineering+ 5 years of related experience, or Masters degree in Electrical Engineering+ 2 years of related experience, or PhD in Electrical Engineering 0+ years of related experience.
• Hands-on experience in ASIC physical design and implementation.
• Experience working with hierarchical floor planning, clock and power distribution, global signal and I/O planning along with physical convergence, timing closure, and hierarchical design methodology.
• Prior experience with power integrity analysis and working on designs >100M gates in advanced nodes (16nm, 14nm, 7nm, 5nm, 3nm, 2nm).

• Experience with Scripting using languages such as TCL, Python and efficient use of AI tools.
• Place & Route experience using tools such as Cadence Innovus or Synopsys FC.
• Synthesis experience including Cadence Genus/Synopsys FC.
• Formal Verification experience using tools such Synopsys Formality or Cadence LEC
• Experience with Static Timing Analysis including tools such as Prime Time-DMSA.
• Experience with Power Integrity including tools such as Apache Redhawk/Voltus
• Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre.

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