Developer; Front End Infrastructure CAD Engineer

Support design, development and verification of Application Specific Integrated Circuit (ASIC) System on Chip (SoC)/Field Programmable Gate Array (FPGA) Intellectual Property (IP) using Verilog, System Verilog, high speed integrated circuit Hardware Description Language (VHDL), Universal Verification Methodology (UVM) and System

C. Improve and optimize Front End Intellectual Property (IP) Design & Verification flows for Application Specific Integrated Circuit (ASIC) / System on Chip (SoC) / Field Programmable Gate Array (FPGA) to boost quality and productivity. Partner with Electronic Design Automation (EDA) tool vendors to troubleshoot issues and streamline integration of new tools in design flows. Scripting and automation using Python, Perl, Bash, csh, tcl.

Manage Compute Infrastructure migrations (e.g. Red Hat Enterprise Linux, SUSE Linux Enterprise Server) and Continuous Integration / Continuous Development automation flows using Jenkins. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won't be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

DISCLAIMER:
The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.

Primary country and city:
United States (US) || Austin (Country/ City) Job details:
Developer Job Stage:
Job Stage 6