Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs

Overview

Our Machine Learning Acceleration (MLA) team designs and develops the SOCs that power todays AI workloads across datacenters worldwide. As an ASIC Design Methodologies and Infrastructure Engineer, you will automate design flows and build large-scale solutions that accelerate silicon development. Were seeking a strong engineer who is passionate about creating design and automation flows that enhance productivity and quality of our design team.

The ideal candidate has proven expertise in RTL design and front-end methodologies, strong software skills, and a drive to improve and automate flows. In this role, you will collaborate with architects, designers, verification engineers, and other cross-functional team members to refine existing design flows and introduce automation solutions that streamline flows and elevate design quality.

• Develop and implement new methodologies and infrastructure to empower design teams to operate efficiently while maintaining high-quality standards.
• Enhance and build design flows to boost the overall productivity of design teams.
• Collaborate with vendors to evaluate and qualify new design tools and updated tool versions.

Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. We deliver cloud solutions that solve challenges that were unimaginable a short time ago. Our custom chips, accelerators, and software stacks enable us to tackle technical challenges that have never been seen before and deliver results that help customers.

• Diverse Experiences:
  We value diverse experiences and encourage candidates to apply even if you do not meet every qualification.
• Work/Life Balance:
  We strive for flexibility to support work-life harmony.
• Inclusive Team Culture:
  We foster inclusion and learning through employee-led affinity groups and events.
• Mentorship & Career Growth:
  We provide knowledge-sharing and career-advancement resources.

Basic Qualifications
- 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience
- 7+ years of digital design in communication systems experience
- 7+ years of full-custom analog or RF layout experience
- 7+ years of wireless communications systems and implementation experience
- 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience
- 7+ years of verification in communication systems experience
- 5+ years of UVM, C, System C, and scripting experience

Preferred Qualifications
- Masters degree or Ph.D. in Electrical Engineering or related field
- Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs

- Experience with modern ASIC/FPGA design and verification tools
- Experience with SOC bring-up and post-silicon validation

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

The base salary range for this position is listed below. The package includes sign-on payments and restricted stock units (RSUs). Final compensation is determined based on factors including experience, qualifications, and location. Amazon offers benefits including health insurance, 401(k) matching, paid time off, and parental leave. Learn more about our benefits at (Use the "Apply for this Job" box below)..

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation during the application and hiring process, including support for the interview or onboarding, please visit  for more information. If the country/region youre applying in isnt listed, contact your Recruiting Partner.

USA, CA, Cupertino -  -  USD annually; USA, TX, Austin -  -  USD annually