Applications Engineering, Sr Staff Engineer-Physical Design, Synthesis

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in the RTL to GDSII flow and you know where things break. Not theoretically, actually. You have debugged synthesis runs that should have closed but didn't, traced timing violations back to their root cause, and explained to a frustrated design team why their netlist won't converge without making them feel like they missed something obvious. You think like a designer but communicate like someone who has sat across from customers who need answers today, not next week.

You are comfortable moving between Fusion Compiler, Prime Time, and Formality without losing sight of what the customer is actually trying to accomplish. When someone sends you a cryptic error log at 4pm, you do not panic. You ask three clarifying questions, reproduce it locally if you can, and either solve it or escalate it to R&D with enough context that they can act on it immediately.

You do not wait for perfect documentation. You read between the lines, test assumptions, and build solutions that work in the real constraints customers face, not the ideal ones described in the user guide. At Synopsys, you will work directly with the teams building the chips that power everything, and what you solve today will unblock someone's tapeout tomorrow.

What You'll Be Doing

* Diagnose and resolve complex technical issues across the full RTL to GDSII flow on live customer designs, working with tools like Fusion Compiler, IC Compiler II, Prime Time, and StarRC

* Deploy new product releases and advanced node methodologies at customer sites, training design teams on implementation strategies, timing closure techniques, and power optimization workflows

* Work directly with R&D to reproduce customer-reported bugs, validate fixes, and influence the technical roadmap based on real deployment feedback

* Review customer design methodologies and provide recommendations on synthesis strategies, floor planning approaches, CTS optimization, and signoff closure

* Partner with Sales and customer technical leads to scope proof-of-concept engagements, evaluate design challenges, and build technical solutions that support new account acquisition

* Script automation workflows in Perl, Tcl, or Python to improve customer productivity, streamline debug processes, or replicate complex design scenarios

* Present technical solutions, design trade-offs, and product capabilities to customer engineering teams and management

The Impact You Will Have

* You will directly unblock critical tapeout schedules by resolving technical issues that would otherwise delay customer milestones by weeks

* Your deployment and training work will accelerate customer adoption of advanced node flows, improving their PPA results and reducing their overall design cycle time

* The feedback you surface from customer engagements will shape product priorities and influence the roadmap for tools used across the semiconductor industry

* You will enable Sales to close strategic accounts by providing the technical credibility and proof points that turn evaluations into partnerships

* Your collaboration with R&D will improve product quality and reliability, reducing the volume of escalations and support cases across the customer base

* You will build long-term customer relationships grounded in trust and technical depth, turning one-time engagements into multi-year partnerships

* The methodologies and scripts you develop will be reused across customer accounts, multiplying your impact beyond individual engagements

What You'll Need

* Typically requires a bachelor's degree and a minimum of 8 years of related experience or an advanced degree and a minimum of 6 years of related experience.

* Hands-on experience across the full RTL to GDSII flow, including…